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authorTerje Bergstrom <tbergstrom@nvidia.com>2015-03-30 14:21:27 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:52:04 -0500
commitc258832b99468adba3cc19a38ba07234cd00de93 (patch)
treed43fb0a39f2c936019558f59c7f25b6271903694 /drivers
parent4de370c12e948ded4f9602869209ed499f103b0c (diff)
gpu: nvgpu: gp10b: Correct steady state CB size
Program steady state CB size to be the HW default. Bug 1626065 Change-Id: If0bdc5a649f307b6adab4e914a6201222b8453f8 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/725106
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h8
2 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 1b7dd405..f91ef1ba 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -110,7 +110,7 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g,
110 gr_gk20a_ctx_patch_write(g, ch_ctx, 110 gr_gk20a_ctx_patch_write(g, ch_ctx,
111 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp + 111 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r() + temp +
112 proj_ppc_in_gpc_stride_v() * ppc_index, 112 proj_ppc_in_gpc_stride_v() * ppc_index,
113 gr->alpha_cb_default_size * gr->pes_tpc_count[ppc_index][gpc_index], 113 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(),
114 patch); 114 patch);
115 115
116 attrib_offset_in_chunk += gr->attrib_cb_size * 116 attrib_offset_in_chunk += gr->attrib_cb_size *
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 72f1d68c..02674d6b 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2174,6 +2174,14 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r(void)
2174{ 2174{
2175 return 0x005030f0; 2175 return 0x005030f0;
2176} 2176}
2177static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v)
2178{
2179 return (v & 0x3fffff) << 0;
2180}
2181static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
2182{
2183 return 0x00030000;
2184}
2177static inline u32 gr_gpccs_falcon_addr_r(void) 2185static inline u32 gr_gpccs_falcon_addr_r(void)
2178{ 2186{
2179 return 0x0041a0ac; 2187 return 0x0041a0ac;