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authorDeepak Nibade <dnibade@nvidia.com>2018-05-08 09:07:09 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-24 07:38:19 -0400
commitc1b78dd65d6d3269c4b25d38fc57975acca02a1a (patch)
tree67258aba47e4c0d1fabd214509fc0dd8aa1e943e /drivers
parent2a0f678257eed156293569a1c00b29fe7d4e956d (diff)
gpu: nvgpu: add HALs to enable/disable hub interrupts
Add below two new HALs gops.fb.enable_hub_intr() to enable hub interrupts gops.fb.disable_hub_intr() to disable hub interrupts Set existing APIs gv11b_fb_enable/disable_hub_intr() to these HALs Call the HALs everywhere instead of calling the APIs directly Jira NVGPUT-44 Change-Id: Id299c6d228733ed365a71be6b180186776cc1306 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1725977 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c2
-rw-r--r--drivers/gpu/nvgpu/gv100/mc_gv100.c4
-rw-r--r--drivers/gpu/nvgpu/gv11b/fb_gv11b.c8
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c2
-rw-r--r--drivers/gpu/nvgpu/gv11b/mc_gv11b.c4
-rw-r--r--drivers/gpu/nvgpu/gv11b/mm_gv11b.c4
7 files changed, 18 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f6318257..01e0511d 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -515,6 +515,10 @@ struct gpu_ops {
515 int (*mem_unlock)(struct gk20a *g); 515 int (*mem_unlock)(struct gk20a *g);
516 int (*init_nvlink)(struct gk20a *g); 516 int (*init_nvlink)(struct gk20a *g);
517 int (*enable_nvlink)(struct gk20a *g); 517 int (*enable_nvlink)(struct gk20a *g);
518 void (*enable_hub_intr)(struct gk20a *g, unsigned int index,
519 unsigned int intr_type);
520 void (*disable_hub_intr)(struct gk20a *g, unsigned int index,
521 unsigned int intr_type);
518 } fb; 522 } fb;
519 struct { 523 struct {
520 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); 524 void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index a4dd09ec..23a3d78f 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -464,6 +464,8 @@ static const struct gpu_ops gv100_ops = {
464 .mem_unlock = gv100_fb_memory_unlock, 464 .mem_unlock = gv100_fb_memory_unlock,
465 .init_nvlink = gv100_fb_init_nvlink, 465 .init_nvlink = gv100_fb_init_nvlink,
466 .enable_nvlink = gv100_fb_enable_nvlink, 466 .enable_nvlink = gv100_fb_enable_nvlink,
467 .enable_hub_intr = gv11b_fb_enable_hub_intr,
468 .disable_hub_intr = gv11b_fb_disable_hub_intr,
467 }, 469 },
468 .clock_gating = { 470 .clock_gating = {
469 .slcg_bus_load_gating_prod = 471 .slcg_bus_load_gating_prod =
diff --git a/drivers/gpu/nvgpu/gv100/mc_gv100.c b/drivers/gpu/nvgpu/gv100/mc_gv100.c
index 31dc97d9..7ed9e6da 100644
--- a/drivers/gpu/nvgpu/gv100/mc_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/mc_gv100.c
@@ -41,7 +41,7 @@ void mc_gv100_intr_enable(struct gk20a *g)
41 0xffffffffU); 41 0xffffffffU);
42 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), 42 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
43 0xffffffffU); 43 0xffffffffU);
44 gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); 44 g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
45 45
46 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = 46 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
47 mc_intr_pfifo_pending_f() | 47 mc_intr_pfifo_pending_f() |
@@ -57,7 +57,7 @@ void mc_gv100_intr_enable(struct gk20a *g)
57 | eng_intr_mask; 57 | eng_intr_mask;
58 58
59 /* TODO: Enable PRI faults for HUB ECC err intr */ 59 /* TODO: Enable PRI faults for HUB ECC err intr */
60 gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); 60 g->ops.fb.enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
61 61
62 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), 62 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
63 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); 63 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
index 47369523..bba47471 100644
--- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c
@@ -1214,7 +1214,7 @@ void gv11b_fb_handle_nonreplay_fault_overflow(struct gk20a *g,
1214static void gv11b_fb_handle_bar2_fault(struct gk20a *g, 1214static void gv11b_fb_handle_bar2_fault(struct gk20a *g,
1215 struct mmu_fault_info *mmfault, u32 fault_status) 1215 struct mmu_fault_info *mmfault, u32 fault_status)
1216{ 1216{
1217 gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, 1217 g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX,
1218 HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); 1218 HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY);
1219 1219
1220 1220
@@ -1235,7 +1235,7 @@ static void gv11b_fb_handle_bar2_fault(struct gk20a *g,
1235 gk20a_channel_put(mmfault->refch); 1235 gk20a_channel_put(mmfault->refch);
1236 mmfault->refch = NULL; 1236 mmfault->refch = NULL;
1237 } 1237 }
1238 gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, 1238 g->ops.fb.enable_hub_intr(g, STALL_REG_INDEX,
1239 HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); 1239 HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY);
1240} 1240}
1241 1241
@@ -1372,7 +1372,7 @@ void gv11b_fb_hub_isr(struct gk20a *g)
1372 nvgpu_info(g, "ecc uncorrected error notify"); 1372 nvgpu_info(g, "ecc uncorrected error notify");
1373 1373
1374 /* disable interrupts during handling */ 1374 /* disable interrupts during handling */
1375 gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, 1375 g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX,
1376 HUB_INTR_TYPE_ECC_UNCORRECTED); 1376 HUB_INTR_TYPE_ECC_UNCORRECTED);
1377 1377
1378 status = gk20a_readl(g, fb_mmu_l2tlb_ecc_status_r()); 1378 status = gk20a_readl(g, fb_mmu_l2tlb_ecc_status_r());
@@ -1388,7 +1388,7 @@ void gv11b_fb_hub_isr(struct gk20a *g)
1388 gv11b_handle_fillunit_ecc_isr(g, status); 1388 gv11b_handle_fillunit_ecc_isr(g, status);
1389 1389
1390 /* re-enable interrupts after handling */ 1390 /* re-enable interrupts after handling */
1391 gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, 1391 g->ops.fb.enable_hub_intr(g, STALL_REG_INDEX,
1392 HUB_INTR_TYPE_ECC_UNCORRECTED); 1392 HUB_INTR_TYPE_ECC_UNCORRECTED);
1393 1393
1394 } 1394 }
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index be8ea76e..5a5aed8e 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -429,6 +429,8 @@ static const struct gpu_ops gv11b_ops = {
429 .tlb_invalidate = gk20a_fb_tlb_invalidate, 429 .tlb_invalidate = gk20a_fb_tlb_invalidate,
430 .hub_isr = gv11b_fb_hub_isr, 430 .hub_isr = gv11b_fb_hub_isr,
431 .mem_unlock = NULL, 431 .mem_unlock = NULL,
432 .enable_hub_intr = gv11b_fb_enable_hub_intr,
433 .disable_hub_intr = gv11b_fb_disable_hub_intr,
432 }, 434 },
433 .clock_gating = { 435 .clock_gating = {
434 .slcg_bus_load_gating_prod = 436 .slcg_bus_load_gating_prod =
diff --git a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
index 6c118ceb..31600828 100644
--- a/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mc_gv11b.c
@@ -41,7 +41,7 @@ void mc_gv11b_intr_enable(struct gk20a *g)
41 0xffffffffU); 41 0xffffffffU);
42 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), 42 gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING),
43 0xffffffffU); 43 0xffffffffU);
44 gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL); 44 g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_ALL);
45 45
46 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] = 46 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING] =
47 mc_intr_pfifo_pending_f() | 47 mc_intr_pfifo_pending_f() |
@@ -56,7 +56,7 @@ void mc_gv11b_intr_enable(struct gk20a *g)
56 | eng_intr_mask; 56 | eng_intr_mask;
57 57
58 /* TODO: Enable PRI faults for HUB ECC err intr */ 58 /* TODO: Enable PRI faults for HUB ECC err intr */
59 gv11b_fb_enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types); 59 g->ops.fb.enable_hub_intr(g, STALL_REG_INDEX, g->mm.hub_intr_types);
60 60
61 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), 61 gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING),
62 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]); 62 g->mc_intr_mask_restore[NVGPU_MC_INTR_STALLING]);
diff --git a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
index f4084ad6..357b15d7 100644
--- a/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/mm_gv11b.c
@@ -76,7 +76,7 @@ void gv11b_mm_fault_info_mem_destroy(struct gk20a *g)
76 76
77 nvgpu_mutex_acquire(&g->mm.hub_isr_mutex); 77 nvgpu_mutex_acquire(&g->mm.hub_isr_mutex);
78 78
79 gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_OTHER | 79 g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_OTHER |
80 HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY); 80 HUB_INTR_TYPE_NONREPLAY | HUB_INTR_TYPE_REPLAY);
81 81
82 nvgpu_kfree(g, g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY]); 82 nvgpu_kfree(g, g->mm.fault_info[FAULT_TYPE_OTHER_AND_NONREPLAY]);
@@ -163,7 +163,7 @@ static void gv11b_mm_mmu_hw_fault_buf_deinit(struct gk20a *g)
163 163
164 nvgpu_log_fn(g, " "); 164 nvgpu_log_fn(g, " ");
165 165
166 gv11b_fb_disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_NONREPLAY | 166 g->ops.fb.disable_hub_intr(g, STALL_REG_INDEX, HUB_INTR_TYPE_NONREPLAY |
167 HUB_INTR_TYPE_REPLAY); 167 HUB_INTR_TYPE_REPLAY);
168 168
169 g->mm.hub_intr_types &= (~(HUB_INTR_TYPE_NONREPLAY | 169 g->mm.hub_intr_types &= (~(HUB_INTR_TYPE_NONREPLAY |