gpu: nvgpu: make tsgid a consistent type

Different units were declaring tsgid as int or u32. This makes everyone
use u32. This change resolves MISRA 10.3 violations for implicit
assingment to different types.

JIRA NVGPU-647

Change-Id: I78660e737acb0dad76dd538e5dd37f4527cf5acd
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1918469
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry picked from commit f5cac144a04a3ef83762ecb2e3f405196beffd68 in
dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/2008513
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

6 files changed, 13 insertions, 11 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 2dd18370..e5ccfcb4 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3528,7 +3528,7 @@ int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
                                 return 0;
                         }
                         if (tsg && ++tsg->num_active_channels) {
-                                set_bit(f->channel[chid].tsgid,
+                                set_bit((int)f->channel[chid].tsgid,
                                         runlist->active_tsgs);
                         }
                 } else {
@@ -3537,7 +3537,7 @@ int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id,
                                 return 0;
                         }
                         if (tsg && --tsg->num_active_channels == 0) {
-                                clear_bit(f->channel[chid].tsgid,
+                                clear_bit((int)f->channel[chid].tsgid,
                                         runlist->active_tsgs);
                         }
                 }
@@ -3642,7 +3642,7 @@ static int __locked_fifo_reschedule_preempt_next(struct channel_gk20a *ch,
         int ret = 0;
         u32 gr_eng_id = 0;
         u32 engstat = 0, ctxstat = 0, fecsstat0 = 0, fecsstat1 = 0;
-        s32 preempt_id = -1;
+        u32 preempt_id;
         u32 preempt_type = 0;
 
         if (1 != gk20a_fifo_get_engine_ids(
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 4541134f..20c13097 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5559,12 +5559,12 @@ int gk20a_gr_handle_notify_pending(struct gk20a *g,
  *
  * Returned channel must be freed with gk20a_channel_put() */
 static struct channel_gk20a *gk20a_gr_get_channel_from_ctx(
-        struct gk20a *g, u32 curr_ctx, int *curr_tsgid)
+        struct gk20a *g, u32 curr_ctx, u32 *curr_tsgid)
 {
         struct fifo_gk20a *f = &g->fifo;
         struct gr_gk20a *gr = &g->gr;
         u32 chid = -1;
-        int tsgid = NVGPU_INVALID_TSG_ID;
+        u32 tsgid = NVGPU_INVALID_TSG_ID;
         u32 i;
         struct channel_gk20a *ret = NULL;
 
@@ -5960,7 +5960,7 @@ int gk20a_gr_isr(struct gk20a *g)
         u32 gr_intr = gk20a_readl(g, gr_intr_r());
         struct channel_gk20a *ch = NULL;
         struct channel_gk20a *fault_ch = NULL;
-        int tsgid = NVGPU_INVALID_TSG_ID;
+        u32 tsgid = NVGPU_INVALID_TSG_ID;
         struct tsg_gk20a *tsg = NULL;
         u32 gr_engine_id;
         u32 global_esr = 0;
@@ -8044,7 +8044,8 @@ static int gr_gk20a_find_priv_offset_in_pm_buffer(struct gk20a *g,
 
 bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch)
 {
-        int curr_gr_ctx, curr_gr_tsgid;
+        int curr_gr_ctx;
+        u32 curr_gr_tsgid;
         struct gk20a *g = ch->g;
         struct channel_gk20a *curr_ch;
         bool ret = false;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h
index cd4fadf8..8d2d9b44 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h
@@ -243,7 +243,7 @@ struct channel_gk20a {
         nvgpu_atomic_t bound;
 
         int chid;
-        int tsgid;
+        u32 tsgid;
         pid_t pid;
         pid_t tgid;
         struct nvgpu_mutex ioctl_lock;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h
index bed84986..e87be90d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h
@@ -28,7 +28,7 @@
 
 #include "gk20a/gr_gk20a.h"
 
-#define NVGPU_INVALID_TSG_ID (-1)
+#define NVGPU_INVALID_TSG_ID (U32_MAX)
 
 struct channel_gk20a;
 
@@ -68,7 +68,7 @@ struct tsg_gk20a {
         unsigned int timeslice_scale;
 
         u32 interleave_level;
-        int tsgid;
+        u32 tsgid;
 
         u32 runlist_id;
         pid_t tgid;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/types.h b/drivers/gpu/nvgpu/include/nvgpu/types.h
index 3295af26..0cb847b6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/types.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/types.h
@@ -65,6 +65,7 @@
  */
 #if !defined(__KERNEL__) && !defined(U8_MAX)
 #define U8_MAX ((u8)255)
+#define U32_MAX         ((u32)~0U)
 #endif
 
 #endif /* NVGPU_TYPES_H */
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index 7bb170da..63d33c6b 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -1713,7 +1713,7 @@ static int nvgpu_profiler_reserve_acquire(struct dbg_session_gk20a *dbg_s,
                 /* TSG: check that another channel in the TSG
                  * doesn't already have the reservation
                  */
-                int my_tsgid = my_prof_obj->ch->tsgid;
+                u32 my_tsgid = my_prof_obj->ch->tsgid;
 
                 nvgpu_list_for_each_entry(prof_obj, &g->profiler_objects,
                                 dbg_profiler_object_data, prof_obj_entry) {