gpu: nvgpu: Make priv_cmd_buf honor num_in_flight jobs

If num_in_flight jobs is set use that to determine the proper
size of the priv_cmd_buf. If num_in_flight is not set then use
the original logic: the priv_cmd_buf is sized based on a worst
case assumption for the GPFIFO.

Also clean up MISRA issues.

Bug 2327792

Change-Id: Ie192caeb6cc48fdcac57e5cbb71c534aeaf46011
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1831095
(cherry picked from commit b9ec592f1d3ce23db736ff9c36eab994fc86ed46)
Reviewed-on: https://git-master.nvidia.com/r/1949220
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: James Norton <jnorton@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 16 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c
index 2097a28e..8af5f5e9 100644
--- a/drivers/gpu/nvgpu/common/fifo/channel.c
+++ b/drivers/gpu/nvgpu/common/fifo/channel.c
@@ -53,7 +53,6 @@
 static void free_channel(struct fifo_gk20a *f, struct channel_gk20a *c);
 static void gk20a_channel_dump_ref_actions(struct channel_gk20a *c);
 
-static int channel_gk20a_alloc_priv_cmdbuf(struct channel_gk20a *c);
 static void channel_gk20a_free_priv_cmdbuf(struct channel_gk20a *c);
 
 static void channel_gk20a_free_prealloc_resources(struct channel_gk20a *c);
@@ -733,13 +732,20 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g,
 
 /* allocate private cmd buffer.
    used for inserting commands before/after user submitted buffers. */
-static int channel_gk20a_alloc_priv_cmdbuf(struct channel_gk20a *c)
+static int channel_gk20a_alloc_priv_cmdbuf(struct channel_gk20a *c,
+        u32 num_in_flight)
 {
         struct gk20a *g = c->g;
         struct vm_gk20a *ch_vm = c->vm;
         struct priv_cmd_queue *q = &c->priv_cmd_q;
         u32 size;
         int err = 0;
+        bool gpfifo_based = false;
+
+        if (num_in_flight == 0U) {
+                num_in_flight = c->gpfifo.entry_num;
+                gpfifo_based = true;
+        }
 
         /*
          * Compute the amount of priv_cmdbuf space we need. In general the worst
@@ -758,8 +764,12 @@ static int channel_gk20a_alloc_priv_cmdbuf(struct channel_gk20a *c)
          *
          *   (gpfifo entry number * (2 / 3) * (8 + 10) * 4 bytes.
          */
-        size = roundup_pow_of_two(c->gpfifo.entry_num *
-                                  2 * 18 * sizeof(u32) / 3);
+        size = num_in_flight * 18U * (u32)sizeof(u32);
+        if (gpfifo_based) {
+                size = 2U * size / 3U;
+        }
+
+        size = PAGE_ALIGN(roundup_pow_of_two(size));
 
         err = nvgpu_dma_alloc_map_sys(ch_vm, size, &q->mem);
         if (err) {
@@ -1230,7 +1240,8 @@ int gk20a_channel_alloc_gpfifo(struct channel_gk20a *c,
                 }
         }
 
-        err = channel_gk20a_alloc_priv_cmdbuf(c);
+        err = channel_gk20a_alloc_priv_cmdbuf(c,
+                                gpfifo_args->num_inflight_jobs);
         if (err) {
                 goto clean_up_prealloc;
         }