diff options
author | Alex Frid <afrid@nvidia.com> | 2017-06-17 00:23:13 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 22:35:47 -0400 |
commit | a34d44b3487b6933e5abf305cccbbd4f15cec05b (patch) | |
tree | 81d234c4b2f4ab2796e0623fb5176f71cccd86e0 /drivers | |
parent | bab823973b0630e2f4515d5aabbe4fb46cdf3195 (diff) |
gpu: nvgpu: Enable GM20B GPCPLL C1 in calibration
Enabled GM20B GPCPLL revision C1 during internal calibration in order
to read calibration status and results.
Bug 1942225
Change-Id: I8fb5f43669bb308de7439792033f640d26f8a3dd
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1504228
(cherry picked from commit a5bed86858fe0e28482bea1a57ecd3085f146ad1)
Reviewed-on: https://git-master/r/1511085
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Samuel Payne <spayne@nvidia.com>
Tested-by: Samuel Payne <spayne@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 8dfc5636..b0e72552 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -454,7 +454,7 @@ static void clk_setup_dvfs_detection(struct gk20a *g, struct pll *gpll) | |||
454 | /* Enable NA/DVFS mode */ | 454 | /* Enable NA/DVFS mode */ |
455 | static int clk_enbale_pll_dvfs(struct gk20a *g) | 455 | static int clk_enbale_pll_dvfs(struct gk20a *g) |
456 | { | 456 | { |
457 | u32 data; | 457 | u32 data, cfg; |
458 | int delay = gpc_pll_params.iddq_exit_delay; /* iddq & calib delay */ | 458 | int delay = gpc_pll_params.iddq_exit_delay; /* iddq & calib delay */ |
459 | struct pll_parms *p = &gpc_pll_params; | 459 | struct pll_parms *p = &gpc_pll_params; |
460 | bool calibrated = p->uvdet_slope && p->uvdet_offs; | 460 | bool calibrated = p->uvdet_slope && p->uvdet_offs; |
@@ -509,6 +509,14 @@ static int clk_enbale_pll_dvfs(struct gk20a *g) | |||
509 | data |= trim_sys_gpcpll_dvfs1_en_dfs_cal_m(); | 509 | data |= trim_sys_gpcpll_dvfs1_en_dfs_cal_m(); |
510 | gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data); | 510 | gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data); |
511 | 511 | ||
512 | /* C1 PLL must be enabled to read internal calibration results */ | ||
513 | if (g->clk.gpc_pll.id == GM20B_GPC_PLL_C1) { | ||
514 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | ||
515 | cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(), | ||
516 | trim_sys_gpcpll_cfg_enable_yes_f()); | ||
517 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); | ||
518 | } | ||
519 | |||
512 | /* Wait for internal calibration done (spec < 2us). */ | 520 | /* Wait for internal calibration done (spec < 2us). */ |
513 | do { | 521 | do { |
514 | data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); | 522 | data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); |
@@ -518,13 +526,22 @@ static int clk_enbale_pll_dvfs(struct gk20a *g) | |||
518 | delay--; | 526 | delay--; |
519 | } while (delay > 0); | 527 | } while (delay > 0); |
520 | 528 | ||
529 | /* Read calibration results */ | ||
530 | data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r()); | ||
531 | data = trim_sys_gpcpll_cfg3_dfs_testout_v(data); | ||
532 | |||
533 | if (g->clk.gpc_pll.id == GM20B_GPC_PLL_C1) { | ||
534 | cfg = set_field(cfg, trim_sys_gpcpll_cfg_enable_m(), | ||
535 | trim_sys_gpcpll_cfg_enable_no_f()); | ||
536 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); | ||
537 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | ||
538 | } | ||
539 | |||
521 | if (delay <= 0) { | 540 | if (delay <= 0) { |
522 | nvgpu_err(g, "GPCPLL calibration timeout"); | 541 | nvgpu_err(g, "GPCPLL calibration timeout"); |
523 | return -ETIMEDOUT; | 542 | return -ETIMEDOUT; |
524 | } | 543 | } |
525 | 544 | ||
526 | data = gk20a_readl(g, trim_sys_gpcpll_cfg3_r()); | ||
527 | data = trim_sys_gpcpll_cfg3_dfs_testout_v(data); | ||
528 | p->uvdet_offs = g->clk.pll_poweron_uv - data * ADC_SLOPE_UV; | 545 | p->uvdet_offs = g->clk.pll_poweron_uv - data * ADC_SLOPE_UV; |
529 | p->uvdet_slope = ADC_SLOPE_UV; | 546 | p->uvdet_slope = ADC_SLOPE_UV; |
530 | return 0; | 547 | return 0; |