diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-17 18:17:23 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-20 17:21:32 -0400 |
commit | a21dcf0bc6bca226582aae45e3a92fe1f7c19e56 (patch) | |
tree | d7407a04e1d72a6ac9ebf4b67004b092a6dd8556 /drivers | |
parent | 9e908d2a8dfb986d2acd024b986ba9917cfe71b1 (diff) |
gpu: nvgpu: Enable CE in GR reset
Enable GRCE when enabling GR. Also use the reset mask read from
device info instead of using the hard coded value.
Change-Id: I4812c32d09ea8b5e07abd1b2c6f1efdbe00cb36e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1149359
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 5 |
2 files changed, 5 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 6ee73ffe..396c5ee5 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -379,8 +379,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
379 | 379 | ||
380 | gk20a_dbg_fn(""); | 380 | gk20a_dbg_fn(""); |
381 | /* enable pmc pfifo */ | 381 | /* enable pmc pfifo */ |
382 | gk20a_reset(g, mc_enable_pfifo_enabled_f() | 382 | gk20a_reset(g, mc_enable_pfifo_enabled_f()); |
383 | | mc_enable_ce2_enabled_f()); | ||
384 | 383 | ||
385 | if (g->ops.clock_gating.slcg_ce2_load_gating_prod) | 384 | if (g->ops.clock_gating.slcg_ce2_load_gating_prod) |
386 | g->ops.clock_gating.slcg_ce2_load_gating_prod(g, | 385 | g->ops.clock_gating.slcg_ce2_load_gating_prod(g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 943b4085..60247da8 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4550,6 +4550,8 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4550 | { | 4550 | { |
4551 | u32 gpfifo_ctrl, pmc_en; | 4551 | u32 gpfifo_ctrl, pmc_en; |
4552 | u32 err = 0; | 4552 | u32 err = 0; |
4553 | struct fifo_engine_info_gk20a *ce_info = | ||
4554 | g->fifo.engine_info + ENGINE_CE2_GK20A; | ||
4553 | 4555 | ||
4554 | /* disable fifo access */ | 4556 | /* disable fifo access */ |
4555 | pmc_en = gk20a_readl(g, mc_enable_r()); | 4557 | pmc_en = gk20a_readl(g, mc_enable_r()); |
@@ -4562,7 +4564,8 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4562 | /* reset gr engine */ | 4564 | /* reset gr engine */ |
4563 | gk20a_reset(g, mc_enable_pgraph_enabled_f() | 4565 | gk20a_reset(g, mc_enable_pgraph_enabled_f() |
4564 | | mc_enable_blg_enabled_f() | 4566 | | mc_enable_blg_enabled_f() |
4565 | | mc_enable_perfmon_enabled_f()); | 4567 | | mc_enable_perfmon_enabled_f() |
4568 | | ce_info->reset_mask); | ||
4566 | 4569 | ||
4567 | gr_gk20a_load_gating_prod(g); | 4570 | gr_gk20a_load_gating_prod(g); |
4568 | /* Disable elcg until it gets enabled later in the init*/ | 4571 | /* Disable elcg until it gets enabled later in the init*/ |