diff options
author | Seema Khowala <seemaj@nvidia.com> | 2018-01-19 17:47:47 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-31 16:23:21 -0500 |
commit | 9beefc45516097db2eabf2887ff66d3334ff9fde (patch) | |
tree | c2b390e4b6ebfb642c87af423a22290561fc60bf /drivers | |
parent | 8e523a9a53088cd6b8645ab2b9ea8b3cd7cd5e9d (diff) |
gpu: nvgpu: add fecs_host_int_enable hal
This will be used to enable fecs interrupts per
chip.
Change-Id: Id99412ca1a9c4caad999c3458b0e9701515db4b9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1642554
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 27 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 19 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 12 |
11 files changed, 52 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8bddad11..3bc10109 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -441,6 +441,7 @@ struct gpu_ops { | |||
441 | u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); | 441 | u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); |
442 | void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, | 442 | void (*dump_ctxsw_stats)(struct gk20a *g, struct vm_gk20a *vm, |
443 | struct nvgpu_gr_ctx *gr_ctx); | 443 | struct nvgpu_gr_ctx *gr_ctx); |
444 | void (*fecs_host_int_enable)(struct gk20a *g); | ||
444 | } gr; | 445 | } gr; |
445 | struct { | 446 | struct { |
446 | void (*init_hw)(struct gk20a *g); | 447 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 68ad7bcd..c7b00500 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4344,6 +4344,16 @@ void gr_gk20a_enable_hww_exceptions(struct gk20a *g) | |||
4344 | gr_memfmt_hww_esr_reset_active_f()); | 4344 | gr_memfmt_hww_esr_reset_active_f()); |
4345 | } | 4345 | } |
4346 | 4346 | ||
4347 | void gr_gk20a_fecs_host_int_enable(struct gk20a *g) | ||
4348 | { | ||
4349 | gk20a_writel(g, gr_fecs_host_int_enable_r(), | ||
4350 | gr_fecs_host_int_enable_ctxsw_intr1_enable_f() | | ||
4351 | gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() | | ||
4352 | gr_fecs_host_int_enable_umimp_firmware_method_enable_f() | | ||
4353 | gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | | ||
4354 | gr_fecs_host_int_enable_watchdog_enable_f()); | ||
4355 | } | ||
4356 | |||
4347 | static int gk20a_init_gr_setup_hw(struct gk20a *g) | 4357 | static int gk20a_init_gr_setup_hw(struct gk20a *g) |
4348 | { | 4358 | { |
4349 | struct gr_gk20a *gr = &g->gr; | 4359 | struct gr_gk20a *gr = &g->gr; |
@@ -4407,12 +4417,7 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g) | |||
4407 | gk20a_writel(g, gr_intr_en_r(), 0xFFFFFFFF); | 4417 | gk20a_writel(g, gr_intr_en_r(), 0xFFFFFFFF); |
4408 | 4418 | ||
4409 | /* enable fecs error interrupts */ | 4419 | /* enable fecs error interrupts */ |
4410 | gk20a_writel(g, gr_fecs_host_int_enable_r(), | 4420 | g->ops.gr.fecs_host_int_enable(g); |
4411 | gr_fecs_host_int_enable_ctxsw_intr1_enable_f() | | ||
4412 | gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() | | ||
4413 | gr_fecs_host_int_enable_umimp_firmware_method_enable_f() | | ||
4414 | gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | | ||
4415 | gr_fecs_host_int_enable_watchdog_enable_f()); | ||
4416 | 4421 | ||
4417 | g->ops.gr.enable_hww_exceptions(g); | 4422 | g->ops.gr.enable_hww_exceptions(g); |
4418 | g->ops.gr.set_hww_esr_report_mask(g); | 4423 | g->ops.gr.set_hww_esr_report_mask(g); |
@@ -5124,15 +5129,9 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | |||
5124 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); | 5129 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); |
5125 | int ret = 0; | 5130 | int ret = 0; |
5126 | 5131 | ||
5127 | gk20a_dbg_fn(""); | ||
5128 | |||
5129 | if (!gr_fecs_intr) | 5132 | if (!gr_fecs_intr) |
5130 | return 0; | 5133 | return 0; |
5131 | 5134 | ||
5132 | nvgpu_err(g, | ||
5133 | "unhandled fecs error interrupt 0x%08x for channel %u", | ||
5134 | gr_fecs_intr, isr_data->chid); | ||
5135 | |||
5136 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { | 5135 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { |
5137 | gk20a_gr_set_error_notifier(g, isr_data, | 5136 | gk20a_gr_set_error_notifier(g, isr_data, |
5138 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); | 5137 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); |
@@ -5141,6 +5140,10 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | |||
5141 | gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)), | 5140 | gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)), |
5142 | isr_data->data_lo); | 5141 | isr_data->data_lo); |
5143 | ret = -1; | 5142 | ret = -1; |
5143 | } else { | ||
5144 | nvgpu_err(g, | ||
5145 | "fecs error interrupt 0x%08x for channel %u", | ||
5146 | gr_fecs_intr, isr_data->chid); | ||
5144 | } | 5147 | } |
5145 | 5148 | ||
5146 | gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); | 5149 | gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index d1c32c03..fa0a4c2d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -732,7 +732,7 @@ static inline void gr_gk20a_free_cyclestats_snapshot_data(struct gk20a *g) | |||
732 | } | 732 | } |
733 | #endif | 733 | #endif |
734 | 734 | ||
735 | 735 | void gr_gk20a_fecs_host_int_enable(struct gk20a *g); | |
736 | int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | 736 | int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, |
737 | struct gr_gk20a_isr_data *isr_data); | 737 | struct gr_gk20a_isr_data *isr_data); |
738 | int gk20a_gr_lock_down_sm(struct gk20a *g, | 738 | int gk20a_gr_lock_down_sm(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 47f666de..58367bcb 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -310,6 +310,7 @@ static const struct gpu_ops gm20b_ops = { | |||
310 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, | 310 | .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs, |
311 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | 311 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, |
312 | .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, | 312 | .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, |
313 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, | ||
313 | }, | 314 | }, |
314 | .fb = { | 315 | .fb = { |
315 | .reset = fb_gk20a_reset, | 316 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index edf1be37..77a1b8f6 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -371,7 +371,8 @@ static const struct gpu_ops gp106_ops = { | |||
371 | .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, | 371 | .set_bes_crop_debug4 = gr_gp10b_set_bes_crop_debug4, |
372 | .create_gr_sysfs = NULL, | 372 | .create_gr_sysfs = NULL, |
373 | .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode, | 373 | .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode, |
374 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode | 374 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, |
375 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, | ||
375 | }, | 376 | }, |
376 | .fb = { | 377 | .fb = { |
377 | .reset = gp106_fb_reset, | 378 | .reset = gp106_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 0fd983a2..462943a0 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -340,6 +340,7 @@ static const struct gpu_ops gp10b_ops = { | |||
340 | .get_max_gfxp_wfi_timeout_count = | 340 | .get_max_gfxp_wfi_timeout_count = |
341 | gr_gp10b_get_max_gfxp_wfi_timeout_count, | 341 | gr_gp10b_get_max_gfxp_wfi_timeout_count, |
342 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, | 342 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, |
343 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, | ||
343 | }, | 344 | }, |
344 | .fb = { | 345 | .fb = { |
345 | .reset = fb_gk20a_reset, | 346 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 22e07288..a2b97520 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -425,6 +425,7 @@ static const struct gpu_ops gv100_ops = { | |||
425 | .handle_tpc_sm_ecc_exception = | 425 | .handle_tpc_sm_ecc_exception = |
426 | gr_gv11b_handle_tpc_sm_ecc_exception, | 426 | gr_gv11b_handle_tpc_sm_ecc_exception, |
427 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | 427 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, |
428 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | ||
428 | }, | 429 | }, |
429 | .fb = { | 430 | .fb = { |
430 | .reset = gv100_fb_reset, | 431 | .reset = gv100_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 857f4944..6b43fcc8 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -321,6 +321,19 @@ void gr_gv11b_enable_hww_exceptions(struct gk20a *g) | |||
321 | gr_memfmt_hww_esr_reset_active_f()); | 321 | gr_memfmt_hww_esr_reset_active_f()); |
322 | } | 322 | } |
323 | 323 | ||
324 | void gr_gv11b_fecs_host_int_enable(struct gk20a *g) | ||
325 | { | ||
326 | gk20a_writel(g, gr_fecs_host_int_enable_r(), | ||
327 | gr_fecs_host_int_enable_ctxsw_intr1_enable_f() | | ||
328 | gr_fecs_host_int_enable_fault_during_ctxsw_enable_f() | | ||
329 | gr_fecs_host_int_enable_umimp_firmware_method_enable_f() | | ||
330 | gr_fecs_host_int_enable_umimp_illegal_method_enable_f() | | ||
331 | gr_fecs_host_int_enable_watchdog_enable_f() | | ||
332 | gr_fecs_host_int_enable_flush_when_busy_enable_f() | | ||
333 | gr_fecs_host_int_enable_ecc_corrected_enable_f() | | ||
334 | gr_fecs_host_int_enable_ecc_uncorrected_enable_f()); | ||
335 | } | ||
336 | |||
324 | void gr_gv11b_enable_exceptions(struct gk20a *g) | 337 | void gr_gv11b_enable_exceptions(struct gk20a *g) |
325 | { | 338 | { |
326 | struct gr_gk20a *gr = &g->gr; | 339 | struct gr_gk20a *gr = &g->gr; |
@@ -2249,13 +2262,13 @@ int gr_gv11b_handle_fecs_error(struct gk20a *g, | |||
2249 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); | 2262 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); |
2250 | int ret; | 2263 | int ret; |
2251 | 2264 | ||
2252 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, ""); | 2265 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr, " "); |
2253 | |||
2254 | ret = gr_gp10b_handle_fecs_error(g, __ch, isr_data); | ||
2255 | 2266 | ||
2256 | /* Handle ECC errors */ | 2267 | /* Handle ECC errors */ |
2257 | gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr); | 2268 | gr_gv11b_handle_fecs_ecc_error(g, gr_fecs_intr); |
2258 | 2269 | ||
2270 | ret = gr_gp10b_handle_fecs_error(g, __ch, isr_data); | ||
2271 | |||
2259 | return ret; | 2272 | return ret; |
2260 | } | 2273 | } |
2261 | 2274 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 774afe56..157c567a 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -133,6 +133,7 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
133 | u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, | 133 | u32 gpc, u32 tpc, u32 sm, u32 global_esr, u32 warp_esr, |
134 | bool sm_debugger_attached, struct channel_gk20a *fault_ch, | 134 | bool sm_debugger_attached, struct channel_gk20a *fault_ch, |
135 | bool *early_exit, bool *ignore_debugger); | 135 | bool *early_exit, bool *ignore_debugger); |
136 | void gr_gv11b_fecs_host_int_enable(struct gk20a *g); | ||
136 | int gr_gv11b_handle_fecs_error(struct gk20a *g, | 137 | int gr_gv11b_handle_fecs_error(struct gk20a *g, |
137 | struct channel_gk20a *__ch, | 138 | struct channel_gk20a *__ch, |
138 | struct gr_gk20a_isr_data *isr_data); | 139 | struct gr_gk20a_isr_data *isr_data); |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 97660917..ec86d74c 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -398,6 +398,7 @@ static const struct gpu_ops gv11b_ops = { | |||
398 | gr_gv11b_get_max_gfxp_wfi_timeout_count, | 398 | gr_gv11b_get_max_gfxp_wfi_timeout_count, |
399 | .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, | 399 | .ecc_init_scrub_reg = gr_gv11b_ecc_init_scrub_reg, |
400 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, | 400 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, |
401 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | ||
401 | }, | 402 | }, |
402 | .fb = { | 403 | .fb = { |
403 | .reset = gv11b_fb_reset, | 404 | .reset = gv11b_fb_reset, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index f40c7585..a4bcce42 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -1988,6 +1988,18 @@ static inline u32 gr_fecs_host_int_enable_watchdog_enable_f(void) | |||
1988 | { | 1988 | { |
1989 | return 0x80000U; | 1989 | return 0x80000U; |
1990 | } | 1990 | } |
1991 | static inline u32 gr_fecs_host_int_enable_flush_when_busy_enable_f(void) | ||
1992 | { | ||
1993 | return 0x100000U; | ||
1994 | } | ||
1995 | static inline u32 gr_fecs_host_int_enable_ecc_corrected_enable_f(void) | ||
1996 | { | ||
1997 | return 0x200000U; | ||
1998 | } | ||
1999 | static inline u32 gr_fecs_host_int_enable_ecc_uncorrected_enable_f(void) | ||
2000 | { | ||
2001 | return 0x400000U; | ||
2002 | } | ||
1991 | static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) | 2003 | static inline u32 gr_fecs_ctxsw_reset_ctl_r(void) |
1992 | { | 2004 | { |
1993 | return 0x00409614U; | 2005 | return 0x00409614U; |