diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-12-07 13:41:13 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-25 17:24:33 -0500 |
commit | 99e808567ca358e0e6d03f4731b81854070266a3 (patch) | |
tree | ad8b851f0a2c50f79be3ebd003f57d35bf705909 /drivers | |
parent | 729403f545c5bc26ce208d38db65962596951e0a (diff) |
gpu: nvgpu: gv100: BOOTSTRAP_GR_FALCONS using RPC
- Created nv_pmu_rpc_struct_acr_bootstrap_gr_falcons struct
- gv100_load_falcon_ucode() function to bootstrap GR
flacons using RPC, wait for INIT_WPR_REGION before
creating & executing BOOTSTRAP_GR_FALCONS RPC.
- Added code to handle BOOTSTRAP_GR_FALCONS ack in
RPC handler
Change-Id: If70dc75bb2789970382853fb001d970a346b2915
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1613316
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/pmu_gv100.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/pmu_gv100.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h | 25 |
5 files changed, 82 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 77acbafc..72337a1d 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -1000,6 +1000,11 @@ static void pmu_rpc_handler(struct gk20a *g, struct pmu_msg *msg, | |||
1000 | "reply NV_PMU_RPC_ID_ACR_INIT_WPR_REGION"); | 1000 | "reply NV_PMU_RPC_ID_ACR_INIT_WPR_REGION"); |
1001 | g->pmu_lsf_pmu_wpr_init_done = 1; | 1001 | g->pmu_lsf_pmu_wpr_init_done = 1; |
1002 | break; | 1002 | break; |
1003 | case NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS: | ||
1004 | nvgpu_pmu_dbg(g, | ||
1005 | "reply NV_PMU_RPC_ID_ACR_BOOTSTRAP_GR_FALCONS"); | ||
1006 | g->pmu_lsf_loaded_falcon_id = 1; | ||
1007 | break; | ||
1003 | } | 1008 | } |
1004 | break; | 1009 | break; |
1005 | case PMU_UNIT_PERFMON_T18X: | 1010 | case PMU_UNIT_PERFMON_T18X: |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index cf9ca9d8..418ff45e 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -574,7 +574,7 @@ static const struct gpu_ops gv100_ops = { | |||
574 | }, | 574 | }, |
575 | .pmu = { | 575 | .pmu = { |
576 | .init_wpr_region = gv100_pmu_init_acr, | 576 | .init_wpr_region = gv100_pmu_init_acr, |
577 | .load_lsfalcon_ucode = gp106_load_falcon_ucode, | 577 | .load_lsfalcon_ucode = gv100_load_falcon_ucode, |
578 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, | 578 | .is_lazy_bootstrap = gp106_is_lazy_bootstrap, |
579 | .is_priv_load = gp106_is_priv_load, | 579 | .is_priv_load = gp106_is_priv_load, |
580 | .prepare_ucode = gp106_prepare_ucode_blob, | 580 | .prepare_ucode = gp106_prepare_ucode_blob, |
diff --git a/drivers/gpu/nvgpu/gv100/pmu_gv100.c b/drivers/gpu/nvgpu/gv100/pmu_gv100.c index 339df6af..113e554b 100644 --- a/drivers/gpu/nvgpu/gv100/pmu_gv100.c +++ b/drivers/gpu/nvgpu/gv100/pmu_gv100.c | |||
@@ -43,3 +43,53 @@ int gv100_pmu_init_acr(struct gk20a *g) | |||
43 | 43 | ||
44 | return status; | 44 | return status; |
45 | } | 45 | } |
46 | |||
47 | int gv100_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | ||
48 | { | ||
49 | struct nvgpu_pmu *pmu = &g->pmu; | ||
50 | struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons rpc; | ||
51 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | ||
52 | int status = 0; | ||
53 | |||
54 | if (falconidmask == 0) | ||
55 | return -EINVAL; | ||
56 | |||
57 | if (falconidmask & ~((1 << LSF_FALCON_ID_FECS) | | ||
58 | (1 << LSF_FALCON_ID_GPCCS))) | ||
59 | return -EINVAL; | ||
60 | |||
61 | g->pmu_lsf_loaded_falcon_id = 0; | ||
62 | /* check whether pmu is ready to bootstrap lsf if not wait for it */ | ||
63 | if (!g->pmu_lsf_pmu_wpr_init_done) { | ||
64 | pmu_wait_message_cond(&g->pmu, | ||
65 | gk20a_get_gr_idle_timeout(g), | ||
66 | &g->pmu_lsf_pmu_wpr_init_done, 1); | ||
67 | /* check again if it still not ready indicate an error */ | ||
68 | if (!g->pmu_lsf_pmu_wpr_init_done) { | ||
69 | nvgpu_err(g, "PMU not ready to load LSF"); | ||
70 | status = -ETIMEDOUT; | ||
71 | goto exit; | ||
72 | } | ||
73 | } | ||
74 | |||
75 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons)); | ||
76 | rpc.falcon_id_mask = falconidmask; | ||
77 | rpc.flags = flags; | ||
78 | rpc.falcon_va_mask = 0; | ||
79 | rpc.wpr_base_virtual.lo = 0; | ||
80 | rpc.wpr_base_virtual.hi = 0; | ||
81 | PMU_RPC_EXECUTE(status, pmu, ACR, BOOTSTRAP_GR_FALCONS, &rpc, 0); | ||
82 | if (status) { | ||
83 | nvgpu_err(g, "Failed to execute RPC, status=0x%x", status); | ||
84 | goto exit; | ||
85 | } | ||
86 | |||
87 | pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), | ||
88 | &g->pmu_lsf_loaded_falcon_id, 1); | ||
89 | |||
90 | if (g->pmu_lsf_loaded_falcon_id != 1) | ||
91 | status = -ETIMEDOUT; | ||
92 | |||
93 | exit: | ||
94 | return status; | ||
95 | } | ||
diff --git a/drivers/gpu/nvgpu/gv100/pmu_gv100.h b/drivers/gpu/nvgpu/gv100/pmu_gv100.h index 5ef34149..4c8b3541 100644 --- a/drivers/gpu/nvgpu/gv100/pmu_gv100.h +++ b/drivers/gpu/nvgpu/gv100/pmu_gv100.h | |||
@@ -28,5 +28,6 @@ | |||
28 | struct gk20a; | 28 | struct gk20a; |
29 | 29 | ||
30 | int gv100_pmu_init_acr(struct gk20a *g); | 30 | int gv100_pmu_init_acr(struct gk20a *g); |
31 | int gv100_load_falcon_ucode(struct gk20a *g, u32 falconidmask); | ||
31 | 32 | ||
32 | #endif /*__PMU_GV100_H_*/ | 33 | #endif /*__PMU_GV100_H_*/ |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h index bc3b1056..c1a4b360 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_acr.h | |||
@@ -131,4 +131,29 @@ struct nv_pmu_rpc_struct_acr_init_wpr_region { | |||
131 | u32 scratch[1]; | 131 | u32 scratch[1]; |
132 | }; | 132 | }; |
133 | 133 | ||
134 | /* | ||
135 | * structure that holds data used to | ||
136 | * execute BOOTSTRAP_GR_FALCONS RPC. | ||
137 | */ | ||
138 | struct nv_pmu_rpc_struct_acr_bootstrap_gr_falcons { | ||
139 | /*[IN/OUT] Must be first field in RPC structure */ | ||
140 | struct nv_pmu_rpc_header hdr; | ||
141 | /* [IN] Mask of falcon IDs @ref LSF_FALCON_ID_<XYZ> */ | ||
142 | u32 falcon_id_mask; | ||
143 | /* | ||
144 | * [IN] Boostrapping flags @ref | ||
145 | * PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_<XYZ> | ||
146 | */ | ||
147 | u32 flags; | ||
148 | /* [IN] Indicate whether the particular falon uses VA */ | ||
149 | u32 falcon_va_mask; | ||
150 | /* | ||
151 | * [IN] WPR Base Address in VA. The Inst Block containing | ||
152 | * this VA should be bound to both PMU and GR falcons | ||
153 | * during the falcon boot | ||
154 | */ | ||
155 | struct falc_u64 wpr_base_virtual; | ||
156 | u32 scratch[1]; | ||
157 | }; | ||
158 | |||
134 | #endif /* _GPMUIFACR_H_ */ | 159 | #endif /* _GPMUIFACR_H_ */ |