gpu: nvgpu: gp10b: clear TEX ECC interrupt

Fix bug in clearing the TEX ECC interrupt.

Bug 200206379

Change-Id: I758b55d20919173de527aeb98143851edcde4eeb
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/1158806
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit

2 files changed, 5 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 339f0413..2ba18410 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -346,7 +346,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
 
         gk20a_writel(g,
                      gr_gpc0_tpc0_tex_m_hww_esr_r() + offset,
-                     esr);
+                     esr | gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f());
 
         return ret;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index 12d84716..0e47c508 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -3694,6 +3694,10 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void)
 {
         return 0x100;
 }
+static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_reset_active_f(void)
+{
+        return 0x40000000;
+}
 static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void)
 {
         return 0x00504648;