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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-11-08 17:29:14 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2016-11-11 14:47:42 -0500
commit8fa5e7c58ac08fdb2432a4791595278d69827fb0 (patch)
tree18d76c47d66d314206315f1d81adcf8513872d09 /drivers
parente580e68f2374b3a0b6226eac7fc4e21dbdcbf22c (diff)
gpu: nvgpu: Remove IOCTL FREE_OBJ_CTX
We have never used the IOCTL FREE_OBJ_CTX. Using it leads to context being only partially available, and can lead to use-after-free. Bug 1834225 Change-Id: I9d2b632ab79760f8186d02e0f35861b3a6aae649 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1250004 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.c12
-rw-r--r--drivers/gpu/nvgpu/gk20a/channel_gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.c23
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c1
-rw-r--r--drivers/gpu/nvgpu/vgpu/gr_vgpu.c22
6 files changed, 0 insertions, 61 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 53ed606d..43a6df0e 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -3467,18 +3467,6 @@ long gk20a_channel_ioctl(struct file *filp,
3467 (struct nvgpu_alloc_obj_ctx_args *)buf); 3467 (struct nvgpu_alloc_obj_ctx_args *)buf);
3468 gk20a_idle(dev); 3468 gk20a_idle(dev);
3469 break; 3469 break;
3470 case NVGPU_IOCTL_CHANNEL_FREE_OBJ_CTX:
3471 err = gk20a_busy(dev);
3472 if (err) {
3473 dev_err(dev,
3474 "%s: failed to host gk20a for ioctl cmd: 0x%x",
3475 __func__, cmd);
3476 break;
3477 }
3478 err = ch->g->ops.gr.free_obj_ctx(ch,
3479 (struct nvgpu_free_obj_ctx_args *)buf);
3480 gk20a_idle(dev);
3481 break;
3482 case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX: 3470 case NVGPU_IOCTL_CHANNEL_ALLOC_GPFIFO_EX:
3483 { 3471 {
3484 struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args = 3472 struct nvgpu_alloc_gpfifo_ex_args *alloc_gpfifo_ex_args =
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index f17128f0..832e03e9 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -155,7 +155,6 @@ struct channel_gk20a {
155 u64 userd_iova; 155 u64 userd_iova;
156 u64 userd_gpu_va; 156 u64 userd_gpu_va;
157 157
158 s32 num_objects;
159 u32 obj_class; /* we support only one obj per channel */ 158 u32 obj_class; /* we support only one obj per channel */
160 159
161 struct priv_cmd_queue priv_cmd_q; 160 struct priv_cmd_queue priv_cmd_q;
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 7699cd53..07752d66 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -196,8 +196,6 @@ struct gpu_ops {
196 void (*free_channel_ctx)(struct channel_gk20a *c); 196 void (*free_channel_ctx)(struct channel_gk20a *c);
197 int (*alloc_obj_ctx)(struct channel_gk20a *c, 197 int (*alloc_obj_ctx)(struct channel_gk20a *c,
198 struct nvgpu_alloc_obj_ctx_args *args); 198 struct nvgpu_alloc_obj_ctx_args *args);
199 int (*free_obj_ctx)(struct channel_gk20a *c,
200 struct nvgpu_free_obj_ctx_args *args);
201 int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr, 199 int (*bind_ctxsw_zcull)(struct gk20a *g, struct gr_gk20a *gr,
202 struct channel_gk20a *c, u64 zcull_va, 200 struct channel_gk20a *c, u64 zcull_va,
203 u32 mode); 201 u32 mode);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 0e8c1884..e6103479 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2957,7 +2957,6 @@ void gk20a_free_channel_ctx(struct channel_gk20a *c)
2957 2957
2958 memset(&c->ch_ctx, 0, sizeof(struct channel_ctx_gk20a)); 2958 memset(&c->ch_ctx, 0, sizeof(struct channel_ctx_gk20a));
2959 2959
2960 c->num_objects = 0;
2961 c->first_init = false; 2960 c->first_init = false;
2962} 2961}
2963 2962
@@ -3169,8 +3168,6 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c,
3169 c->first_init = true; 3168 c->first_init = true;
3170 } 3169 }
3171 3170
3172 c->num_objects++;
3173
3174 gk20a_dbg_fn("done"); 3171 gk20a_dbg_fn("done");
3175 return 0; 3172 return 0;
3176out: 3173out:
@@ -3182,25 +3179,6 @@ out:
3182 return err; 3179 return err;
3183} 3180}
3184 3181
3185int gk20a_free_obj_ctx(struct channel_gk20a *c,
3186 struct nvgpu_free_obj_ctx_args *args)
3187{
3188 gk20a_dbg_fn("");
3189
3190 if (c->num_objects == 0)
3191 return 0;
3192
3193 c->num_objects--;
3194
3195 if (c->num_objects == 0) {
3196 c->first_init = false;
3197 gk20a_disable_channel(c);
3198 gr_gk20a_free_channel_patch_ctx(c);
3199 }
3200
3201 return 0;
3202}
3203
3204int gk20a_comptag_allocator_init(struct gk20a_comptag_allocator *allocator, 3182int gk20a_comptag_allocator_init(struct gk20a_comptag_allocator *allocator,
3205 unsigned long size) 3183 unsigned long size)
3206{ 3184{
@@ -9082,7 +9060,6 @@ void gk20a_init_gr_ops(struct gpu_ops *gops)
9082 gops->gr.get_gpc_tpc_mask = gr_gk20a_get_gpc_tpc_mask; 9060 gops->gr.get_gpc_tpc_mask = gr_gk20a_get_gpc_tpc_mask;
9083 gops->gr.free_channel_ctx = gk20a_free_channel_ctx; 9061 gops->gr.free_channel_ctx = gk20a_free_channel_ctx;
9084 gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; 9062 gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx;
9085 gops->gr.free_obj_ctx = gk20a_free_obj_ctx;
9086 gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; 9063 gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull;
9087 gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; 9064 gops->gr.get_zcull_info = gr_gk20a_get_zcull_info;
9088 gops->gr.is_tpc_addr = gr_gk20a_is_tpc_addr; 9065 gops->gr.is_tpc_addr = gr_gk20a_is_tpc_addr;
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 37b9737b..56812fa6 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1534,7 +1534,6 @@ void gm20b_init_gr(struct gpu_ops *gops)
1534 gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask; 1534 gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask;
1535 gops->gr.free_channel_ctx = gk20a_free_channel_ctx; 1535 gops->gr.free_channel_ctx = gk20a_free_channel_ctx;
1536 gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx; 1536 gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx;
1537 gops->gr.free_obj_ctx = gk20a_free_obj_ctx;
1538 gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; 1537 gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull;
1539 gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; 1538 gops->gr.get_zcull_info = gr_gk20a_get_zcull_info;
1540 gops->gr.is_tpc_addr = gr_gm20b_is_tpc_addr; 1539 gops->gr.is_tpc_addr = gr_gm20b_is_tpc_addr;
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 89223091..01f5e1a5 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -421,7 +421,6 @@ static void vgpu_gr_free_channel_ctx(struct channel_gk20a *c)
421 421
422 memset(&c->ch_ctx, 0, sizeof(struct channel_ctx_gk20a)); 422 memset(&c->ch_ctx, 0, sizeof(struct channel_ctx_gk20a));
423 423
424 c->num_objects = 0;
425 c->first_init = false; 424 c->first_init = false;
426} 425}
427 426
@@ -586,8 +585,6 @@ static int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c,
586 c->first_init = true; 585 c->first_init = true;
587 } 586 }
588 587
589 c->num_objects++;
590
591 gk20a_dbg_fn("done"); 588 gk20a_dbg_fn("done");
592 return 0; 589 return 0;
593out: 590out:
@@ -599,24 +596,6 @@ out:
599 return err; 596 return err;
600} 597}
601 598
602static int vgpu_gr_free_obj_ctx(struct channel_gk20a *c,
603 struct nvgpu_free_obj_ctx_args *args)
604{
605 gk20a_dbg_fn("");
606
607 if (c->num_objects == 0)
608 return 0;
609
610 c->num_objects--;
611
612 if (c->num_objects == 0) {
613 c->first_init = false;
614 gk20a_disable_channel(c);
615 }
616
617 return 0;
618}
619
620static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr) 599static int vgpu_gr_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
621{ 600{
622 struct vgpu_priv_data *priv = vgpu_get_priv_data(g); 601 struct vgpu_priv_data *priv = vgpu_get_priv_data(g);
@@ -1073,7 +1052,6 @@ void vgpu_init_gr_ops(struct gpu_ops *gops)
1073 gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch; 1052 gops->gr.detect_sm_arch = vgpu_gr_detect_sm_arch;
1074 gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx; 1053 gops->gr.free_channel_ctx = vgpu_gr_free_channel_ctx;
1075 gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx; 1054 gops->gr.alloc_obj_ctx = vgpu_gr_alloc_obj_ctx;
1076 gops->gr.free_obj_ctx = vgpu_gr_free_obj_ctx;
1077 gops->gr.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx; 1055 gops->gr.alloc_gr_ctx = vgpu_gr_alloc_gr_ctx;
1078 gops->gr.free_gr_ctx = vgpu_gr_free_gr_ctx; 1056 gops->gr.free_gr_ctx = vgpu_gr_free_gr_ctx;
1079 gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull; 1057 gops->gr.bind_ctxsw_zcull = vgpu_gr_bind_ctxsw_zcull;