diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-12 00:53:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-20 03:20:56 -0400 |
commit | 8b571de4563b83352097474c5f7157ea6623a97f (patch) | |
tree | fe87ccc9dc727d6120c2e51e6392494416ce6d00 /drivers | |
parent | 357e3d4d388bef0556239412ab46dd01c3bbac2e (diff) |
gpu: nvgpu: gv11b: implement init_gpc_mmu
- Created HAL to configure gpc mmu unit for gv11b.
- Earlier chips needs writes to NV_PGRAPH_PRI_GPCS_MMU_NUM_ACTIVE_LTCS
register to know supported number of LTCS by reading NUM_ACTIVE_LTCS
but gv11b support auto update from fuse upon reset, so skipped
LTCS update for GPCS & skipping helps to fix compression failure
issue.
Bug 1950234
Change-Id: I628af7d1399e4fe3126895e3a703a19147f7a12f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1517733
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 36 |
1 files changed, 35 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index fab2ae9a..3450bf05 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -45,10 +45,10 @@ | |||
45 | #include <nvgpu/hw/gv11b/hw_proj_gv11b.h> | 45 | #include <nvgpu/hw/gv11b/hw_proj_gv11b.h> |
46 | #include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h> | 46 | #include <nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h> |
47 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> | 47 | #include <nvgpu/hw/gv11b/hw_mc_gv11b.h> |
48 | #include <nvgpu/hw/gv11b/hw_gr_gv11b.h> | ||
49 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> | 48 | #include <nvgpu/hw/gv11b/hw_ram_gv11b.h> |
50 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> | 49 | #include <nvgpu/hw/gv11b/hw_pbdma_gv11b.h> |
51 | #include <nvgpu/hw/gv11b/hw_therm_gv11b.h> | 50 | #include <nvgpu/hw/gv11b/hw_therm_gv11b.h> |
51 | #include <nvgpu/hw/gv11b/hw_fb_gv11b.h> | ||
52 | 52 | ||
53 | static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) | 53 | static bool gr_gv11b_is_valid_class(struct gk20a *g, u32 class_num) |
54 | { | 54 | { |
@@ -3568,6 +3568,39 @@ static u32 gv11b_gr_get_egpc_base(struct gk20a *g) | |||
3568 | return EGPC_PRI_BASE; | 3568 | return EGPC_PRI_BASE; |
3569 | } | 3569 | } |
3570 | 3570 | ||
3571 | static void gr_gv11b_init_gpc_mmu(struct gk20a *g) | ||
3572 | { | ||
3573 | u32 temp; | ||
3574 | |||
3575 | nvgpu_log_info(g, "initialize gpc mmu"); | ||
3576 | |||
3577 | if (!g->ops.privsecurity) { | ||
3578 | /* Bypass MMU check for non-secure boot. For | ||
3579 | * secure-boot,this register write has no-effect */ | ||
3580 | gk20a_writel(g, fb_priv_mmu_phy_secure_r(), 0xffffffff); | ||
3581 | } | ||
3582 | temp = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
3583 | temp &= gr_gpcs_pri_mmu_ctrl_vm_pg_size_m() | | ||
3584 | gr_gpcs_pri_mmu_ctrl_use_pdb_big_page_size_m() | | ||
3585 | gr_gpcs_pri_mmu_ctrl_vol_fault_m() | | ||
3586 | gr_gpcs_pri_mmu_ctrl_comp_fault_m() | | ||
3587 | gr_gpcs_pri_mmu_ctrl_miss_gran_m() | | ||
3588 | gr_gpcs_pri_mmu_ctrl_cache_mode_m() | | ||
3589 | gr_gpcs_pri_mmu_ctrl_mmu_aperture_m() | | ||
3590 | gr_gpcs_pri_mmu_ctrl_mmu_vol_m() | | ||
3591 | gr_gpcs_pri_mmu_ctrl_mmu_disable_m(); | ||
3592 | gk20a_writel(g, gr_gpcs_pri_mmu_ctrl_r(), temp); | ||
3593 | gk20a_writel(g, gr_gpcs_pri_mmu_pm_unit_mask_r(), 0); | ||
3594 | gk20a_writel(g, gr_gpcs_pri_mmu_pm_req_mask_r(), 0); | ||
3595 | |||
3596 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), | ||
3597 | gk20a_readl(g, fb_mmu_debug_ctrl_r())); | ||
3598 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_wr_r(), | ||
3599 | gk20a_readl(g, fb_mmu_debug_wr_r())); | ||
3600 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_rd_r(), | ||
3601 | gk20a_readl(g, fb_mmu_debug_rd_r())); | ||
3602 | } | ||
3603 | |||
3571 | void gv11b_init_gr(struct gpu_ops *gops) | 3604 | void gv11b_init_gr(struct gpu_ops *gops) |
3572 | { | 3605 | { |
3573 | gp10b_init_gr(gops); | 3606 | gp10b_init_gr(gops); |
@@ -3664,4 +3697,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
3664 | gops->gr.get_egpc_base = gv11b_gr_get_egpc_base; | 3697 | gops->gr.get_egpc_base = gv11b_gr_get_egpc_base; |
3665 | gops->gr.is_egpc_addr = gv11b_gr_pri_is_egpc_addr; | 3698 | gops->gr.is_egpc_addr = gv11b_gr_pri_is_egpc_addr; |
3666 | gops->gr.is_etpc_addr = gv11b_gr_pri_is_etpc_addr; | 3699 | gops->gr.is_etpc_addr = gv11b_gr_pri_is_etpc_addr; |
3700 | gops->gr.init_gpc_mmu = gr_gv11b_init_gpc_mmu; | ||
3667 | } | 3701 | } |