gpu: nvgpu: gm20b: use gpc_mmu to check debug mode

Bug 1534793

Change-Id: I8a4c35914b58dd13a7c10c668de9d4662d947d8c
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/441377
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

6 files changed, 21 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index e2b8a12e..b1cd50ea 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -862,7 +862,7 @@ static bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
         /* channel recovery is only deferred if an sm debugger
            is attached and has MMU debug mode is enabled */
         if (!gk20a_gr_sm_debugger_attached(g) ||
-            !gk20a_mm_mmu_debug_mode_enabled(g))
+            !g->ops.mm.is_debug_mode_enabled(g))
                 return false;
 
         /* if this fault is fake (due to RC recovery), don't defer recovery */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index b5ef3f0d..77300203 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -239,6 +239,7 @@ struct gpu_ops {
                                u32 num_pages, u32 pgsz_idx);
                 void (*clear_sparse)(struct vm_gk20a *vm, u64 vaddr,
                                u64 size, u32 pgsz_idx);
+                bool (*is_debug_mode_enabled)(struct gk20a *g);
         } mm;
         struct {
                 int (*prepare_ucode)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 3298a383..a2832a9f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5267,7 +5267,7 @@ static int gk20a_gr_lock_down_sm(struct gk20a *g, u32 global_esr_mask)
         unsigned long end_jiffies = jiffies +
                 msecs_to_jiffies(gk20a_get_gr_idle_timeout(g));
         u32 delay = GR_IDLE_CHECK_DEFAULT;
-        bool mmu_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled(g);
+        bool mmu_debug_mode_enabled = g->ops.mm.is_debug_mode_enabled(g);
         u32 dbgr_control0;
 
         gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "locking down SM");
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 93a29b13..92095162 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -3111,5 +3111,6 @@ void gk20a_init_mm(struct gpu_ops *gops)
         gops->mm.set_sparse = gk20a_vm_put_sparse;
         gops->mm.put_empty = gk20a_vm_put_empty;
         gops->mm.clear_sparse = gk20a_vm_clear_sparse;
+        gops->mm.is_debug_mode_enabled = gk20a_mm_mmu_debug_mode_enabled;
 }
 
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index eb6cf4ad..21a46d33 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -3210,6 +3210,14 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
 {
         return 0x004188b0;
 }
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
+{
+        return (r >> 16) & 0x1;
+}
+static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
+{
+        return 0x00000001;
+}
 static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
 {
         return 0x004188b4;
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index a16f4adf..ac82d56a 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -18,6 +18,7 @@
 #include "mm_gm20b.h"
 #include "hw_gmmu_gm20b.h"
 #include "hw_fb_gm20b.h"
+#include "hw_gr_gm20b.h"
 
 static const u32 gmmu_page_sizes[gmmu_nr_page_sizes] = { SZ_4K, SZ_128K };
 static const u32 gmmu_page_shifts[gmmu_nr_page_sizes] = { 12, 17 };
@@ -314,8 +315,16 @@ void gm20b_vm_clear_sparse(struct vm_gk20a *vm, u64 vaddr,
         return;
 }
 
+bool gm20b_mm_mmu_debug_mode_enabled(struct gk20a *g)
+{
+        u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
+        return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) ==
+                gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v();
+}
+
 void gm20b_init_mm(struct gpu_ops *gops)
 {
         gops->mm.set_sparse = gm20b_vm_put_sparse;
         gops->mm.clear_sparse = gm20b_vm_clear_sparse;
+        gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled;
 }