diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-12-27 16:04:17 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-01-02 16:53:09 -0500 |
commit | 86691b59c6fae2b091855c0f4d44079cad8529b1 (patch) | |
tree | c9fd2914ed052771980298f5e77bd43d7c430ec9 /drivers | |
parent | 14fa8207e2f7feb36f8fa284b94859e05136eb0f (diff) |
gpu: nvgpu: Remove bare channel scheduling
Remove scheduling IOCTL implementations for bare channels. Also
removes code that constructs bare channels in runlist.
Bug 1842197
Change-Id: I6e833b38e24a2f2c45c7993edf939d365eaf41f0
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1627326
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
19 files changed, 22 insertions, 257 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/debug_fifo.c b/drivers/gpu/nvgpu/common/linux/debug_fifo.c index 94a16b70..ad157ee7 100644 --- a/drivers/gpu/nvgpu/common/linux/debug_fifo.c +++ b/drivers/gpu/nvgpu/common/linux/debug_fifo.c | |||
@@ -81,16 +81,16 @@ static int gk20a_fifo_sched_debugfs_seq_show( | |||
81 | return ret; | 81 | return ret; |
82 | 82 | ||
83 | if (gk20a_channel_get(ch)) { | 83 | if (gk20a_channel_get(ch)) { |
84 | if (gk20a_is_channel_marked_as_tsg(ch)) | 84 | tsg = tsg_gk20a_from_ch(ch); |
85 | tsg = &f->tsg[ch->tsgid]; | ||
86 | 85 | ||
87 | seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d %-8d\n", | 86 | if (tsg) |
87 | seq_printf(s, "%-8d %-8d %-8d %-9d %-8d %-10d %-8d %-8d\n", | ||
88 | ch->chid, | 88 | ch->chid, |
89 | ch->tsgid, | 89 | ch->tsgid, |
90 | ch->tgid, | 90 | ch->tgid, |
91 | tsg ? tsg->timeslice_us : ch->timeslice_us, | 91 | tsg->timeslice_us, |
92 | ch->timeout_ms_max, | 92 | ch->timeout_ms_max, |
93 | tsg ? tsg->interleave_level : ch->interleave_level, | 93 | tsg->interleave_level, |
94 | ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->graphics_preempt_mode : U32_MAX, | 94 | ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->graphics_preempt_mode : U32_MAX, |
95 | ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->compute_preempt_mode : U32_MAX); | 95 | ch->ch_ctx.gr_ctx ? ch->ch_ctx.gr_ctx->compute_preempt_mode : U32_MAX); |
96 | gk20a_channel_put(ch); | 96 | gk20a_channel_put(ch); |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c index 65d560c7..94501a89 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c | |||
@@ -76,11 +76,15 @@ static void gk20a_channel_trace_sched_param( | |||
76 | const char *compute_preempt_mode), | 76 | const char *compute_preempt_mode), |
77 | struct channel_gk20a *ch) | 77 | struct channel_gk20a *ch) |
78 | { | 78 | { |
79 | struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch); | ||
80 | |||
81 | if (!tsg) | ||
82 | return; | ||
83 | |||
79 | (trace)(ch->chid, ch->tsgid, ch->pid, | 84 | (trace)(ch->chid, ch->tsgid, ch->pid, |
80 | gk20a_is_channel_marked_as_tsg(ch) ? | 85 | tsg_gk20a_from_ch(ch)->timeslice_us, |
81 | tsg_gk20a_from_ch(ch)->timeslice_us : ch->timeslice_us, | ||
82 | ch->timeout_ms_max, | 86 | ch->timeout_ms_max, |
83 | gk20a_fifo_interleave_level_name(ch->interleave_level), | 87 | gk20a_fifo_interleave_level_name(tsg->interleave_level), |
84 | gr_gk20a_graphics_preempt_mode_name(ch->ch_ctx.gr_ctx ? | 88 | gr_gk20a_graphics_preempt_mode_name(ch->ch_ctx.gr_ctx ? |
85 | ch->ch_ctx.gr_ctx->graphics_preempt_mode : 0), | 89 | ch->ch_ctx.gr_ctx->graphics_preempt_mode : 0), |
86 | gr_gk20a_compute_preempt_mode_name(ch->ch_ctx.gr_ctx ? | 90 | gr_gk20a_compute_preempt_mode_name(ch->ch_ctx.gr_ctx ? |
@@ -795,28 +799,6 @@ u32 nvgpu_get_common_runlist_level(u32 level) | |||
795 | return level; | 799 | return level; |
796 | } | 800 | } |
797 | 801 | ||
798 | static int gk20a_ioctl_channel_set_runlist_interleave(struct channel_gk20a *ch, | ||
799 | u32 level) | ||
800 | { | ||
801 | int err = 0; | ||
802 | |||
803 | err = gk20a_busy(ch->g); | ||
804 | if (err) { | ||
805 | nvgpu_err(ch->g, "failed to power on, %d", err); | ||
806 | goto fail; | ||
807 | } | ||
808 | |||
809 | level = nvgpu_get_common_runlist_level(level); | ||
810 | err = gk20a_channel_set_runlist_interleave(ch, level); | ||
811 | |||
812 | gk20a_idle(ch->g); | ||
813 | gk20a_channel_trace_sched_param( | ||
814 | trace_gk20a_channel_set_runlist_interleave, ch); | ||
815 | |||
816 | fail: | ||
817 | return err; | ||
818 | } | ||
819 | |||
820 | static u32 nvgpu_obj_ctx_user_flags_to_common_flags(u32 user_flags) | 802 | static u32 nvgpu_obj_ctx_user_flags_to_common_flags(u32 user_flags) |
821 | { | 803 | { |
822 | u32 flags = 0; | 804 | u32 flags = 0; |
@@ -1229,29 +1211,6 @@ long gk20a_channel_ioctl(struct file *filp, | |||
1229 | err = gk20a_channel_set_wdt_status(ch, | 1211 | err = gk20a_channel_set_wdt_status(ch, |
1230 | (struct nvgpu_channel_wdt_args *)buf); | 1212 | (struct nvgpu_channel_wdt_args *)buf); |
1231 | break; | 1213 | break; |
1232 | case NVGPU_IOCTL_CHANNEL_SET_RUNLIST_INTERLEAVE: | ||
1233 | err = gk20a_ioctl_channel_set_runlist_interleave(ch, | ||
1234 | ((struct nvgpu_runlist_interleave_args *)buf)->level); | ||
1235 | break; | ||
1236 | case NVGPU_IOCTL_CHANNEL_SET_TIMESLICE: | ||
1237 | err = gk20a_busy(ch->g); | ||
1238 | if (err) { | ||
1239 | dev_err(dev, | ||
1240 | "%s: failed to host gk20a for ioctl cmd: 0x%x", | ||
1241 | __func__, cmd); | ||
1242 | break; | ||
1243 | } | ||
1244 | err = ch->g->ops.fifo.channel_set_timeslice(ch, | ||
1245 | ((struct nvgpu_timeslice_args *)buf)->timeslice_us); | ||
1246 | |||
1247 | gk20a_idle(ch->g); | ||
1248 | gk20a_channel_trace_sched_param( | ||
1249 | trace_gk20a_channel_set_timeslice, ch); | ||
1250 | break; | ||
1251 | case NVGPU_IOCTL_CHANNEL_GET_TIMESLICE: | ||
1252 | ((struct nvgpu_timeslice_args *)buf)->timeslice_us = | ||
1253 | gk20a_channel_get_timeslice(ch); | ||
1254 | break; | ||
1255 | case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE: | 1214 | case NVGPU_IOCTL_CHANNEL_SET_PREEMPTION_MODE: |
1256 | err = nvgpu_ioctl_channel_set_preemption_mode(ch, | 1215 | err = nvgpu_ioctl_channel_set_preemption_mode(ch, |
1257 | ((struct nvgpu_preemption_mode_args *)buf)->graphics_preempt_mode, | 1216 | ((struct nvgpu_preemption_mode_args *)buf)->graphics_preempt_mode, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c index e06b41da..6b8c630b 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.c | |||
@@ -604,8 +604,8 @@ int vgpu_fifo_wait_engine_idle(struct gk20a *g) | |||
604 | return 0; | 604 | return 0; |
605 | } | 605 | } |
606 | 606 | ||
607 | static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, | 607 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, |
608 | u32 tsgid, | 608 | u32 id, |
609 | u32 runlist_id, | 609 | u32 runlist_id, |
610 | u32 new_level) | 610 | u32 new_level) |
611 | { | 611 | { |
@@ -618,62 +618,13 @@ static int vgpu_fifo_tsg_set_runlist_interleave(struct gk20a *g, | |||
618 | 618 | ||
619 | msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE; | 619 | msg.cmd = TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE; |
620 | msg.handle = vgpu_get_handle(g); | 620 | msg.handle = vgpu_get_handle(g); |
621 | p->tsg_id = tsgid; | 621 | p->tsg_id = id; |
622 | p->level = new_level; | ||
623 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
624 | WARN_ON(err || msg.ret); | ||
625 | return err ? err : msg.ret; | ||
626 | } | ||
627 | |||
628 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | ||
629 | u32 id, | ||
630 | bool is_tsg, | ||
631 | u32 runlist_id, | ||
632 | u32 new_level) | ||
633 | { | ||
634 | struct tegra_vgpu_cmd_msg msg; | ||
635 | struct tegra_vgpu_channel_runlist_interleave_params *p = | ||
636 | &msg.params.channel_interleave; | ||
637 | struct channel_gk20a *ch; | ||
638 | int err; | ||
639 | |||
640 | gk20a_dbg_fn(""); | ||
641 | |||
642 | if (is_tsg) | ||
643 | return vgpu_fifo_tsg_set_runlist_interleave(g, id, | ||
644 | runlist_id, new_level); | ||
645 | |||
646 | ch = &g->fifo.channel[id]; | ||
647 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE; | ||
648 | msg.handle = vgpu_get_handle(ch->g); | ||
649 | p->handle = ch->virt_ctx; | ||
650 | p->level = new_level; | 622 | p->level = new_level; |
651 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | 623 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); |
652 | WARN_ON(err || msg.ret); | 624 | WARN_ON(err || msg.ret); |
653 | return err ? err : msg.ret; | 625 | return err ? err : msg.ret; |
654 | } | 626 | } |
655 | 627 | ||
656 | int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | ||
657 | { | ||
658 | struct tegra_vgpu_cmd_msg msg; | ||
659 | struct tegra_vgpu_channel_timeslice_params *p = | ||
660 | &msg.params.channel_timeslice; | ||
661 | int err; | ||
662 | |||
663 | gk20a_dbg_fn(""); | ||
664 | |||
665 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE; | ||
666 | msg.handle = vgpu_get_handle(ch->g); | ||
667 | p->handle = ch->virt_ctx; | ||
668 | p->timeslice_us = timeslice; | ||
669 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
670 | err = err ? err : msg.ret; | ||
671 | WARN_ON(err); | ||
672 | if (!err) | ||
673 | ch->timeslice_us = p->timeslice_us; | ||
674 | return err; | ||
675 | } | ||
676 | |||
677 | int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, | 628 | int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, |
678 | u32 err_code, bool verbose) | 629 | u32 err_code, bool verbose) |
679 | { | 630 | { |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h index 5aefb356..92789ddd 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/common/linux/vgpu/fifo_vgpu.h | |||
@@ -42,7 +42,6 @@ int vgpu_fifo_update_runlist(struct gk20a *g, u32 runlist_id, | |||
42 | int vgpu_fifo_wait_engine_idle(struct gk20a *g); | 42 | int vgpu_fifo_wait_engine_idle(struct gk20a *g); |
43 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, | 43 | int vgpu_fifo_set_runlist_interleave(struct gk20a *g, |
44 | u32 id, | 44 | u32 id, |
45 | bool is_tsg, | ||
46 | u32 runlist_id, | 45 | u32 runlist_id, |
47 | u32 new_level); | 46 | u32 new_level); |
48 | int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); | 47 | int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice); |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index 6f50dbb8..74fa65f3 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -260,7 +260,6 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
260 | .alloc_inst = vgpu_channel_alloc_inst, | 260 | .alloc_inst = vgpu_channel_alloc_inst, |
261 | .free_inst = vgpu_channel_free_inst, | 261 | .free_inst = vgpu_channel_free_inst, |
262 | .setup_ramfc = vgpu_channel_setup_ramfc, | 262 | .setup_ramfc = vgpu_channel_setup_ramfc, |
263 | .channel_set_timeslice = vgpu_channel_set_timeslice, | ||
264 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | 263 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, |
265 | .setup_userd = gk20a_fifo_setup_userd, | 264 | .setup_userd = gk20a_fifo_setup_userd, |
266 | .userd_gp_get = gk20a_fifo_userd_gp_get, | 265 | .userd_gp_get = gk20a_fifo_userd_gp_get, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 31608200..66ef6e00 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -290,7 +290,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
290 | .alloc_inst = vgpu_channel_alloc_inst, | 290 | .alloc_inst = vgpu_channel_alloc_inst, |
291 | .free_inst = vgpu_channel_free_inst, | 291 | .free_inst = vgpu_channel_free_inst, |
292 | .setup_ramfc = vgpu_channel_setup_ramfc, | 292 | .setup_ramfc = vgpu_channel_setup_ramfc, |
293 | .channel_set_timeslice = vgpu_channel_set_timeslice, | ||
294 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | 293 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, |
295 | .setup_userd = gk20a_fifo_setup_userd, | 294 | .setup_userd = gk20a_fifo_setup_userd, |
296 | .userd_gp_get = gk20a_fifo_userd_gp_get, | 295 | .userd_gp_get = gk20a_fifo_userd_gp_get, |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c index b41d9dc3..1523c2de 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -331,7 +331,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
331 | .alloc_inst = vgpu_channel_alloc_inst, | 331 | .alloc_inst = vgpu_channel_alloc_inst, |
332 | .free_inst = vgpu_channel_free_inst, | 332 | .free_inst = vgpu_channel_free_inst, |
333 | .setup_ramfc = vgpu_channel_setup_ramfc, | 333 | .setup_ramfc = vgpu_channel_setup_ramfc, |
334 | .channel_set_timeslice = vgpu_channel_set_timeslice, | ||
335 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, | 334 | .default_timeslice_us = vgpu_fifo_default_timeslice_us, |
336 | .setup_userd = gk20a_fifo_setup_userd, | 335 | .setup_userd = gk20a_fifo_setup_userd, |
337 | .userd_gp_get = gv11b_userd_gp_get, | 336 | .userd_gp_get = gv11b_userd_gp_get, |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 5e2fc6b3..ec20a679 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -504,7 +504,7 @@ u32 gk20a_ce_create_context(struct gk20a *g, | |||
504 | 504 | ||
505 | /* -1 means default channel timeslice value */ | 505 | /* -1 means default channel timeslice value */ |
506 | if (timeslice != -1) { | 506 | if (timeslice != -1) { |
507 | err = gk20a_fifo_set_timeslice(ce_ctx->ch, timeslice); | 507 | err = gk20a_fifo_tsg_set_timeslice(ce_ctx->tsg, timeslice); |
508 | if (err) { | 508 | if (err) { |
509 | nvgpu_err(g, | 509 | nvgpu_err(g, |
510 | "ce: could not set the channel timeslice value for CE context"); | 510 | "ce: could not set the channel timeslice value for CE context"); |
@@ -514,7 +514,8 @@ u32 gk20a_ce_create_context(struct gk20a *g, | |||
514 | 514 | ||
515 | /* -1 means default channel runlist level */ | 515 | /* -1 means default channel runlist level */ |
516 | if (runlist_level != -1) { | 516 | if (runlist_level != -1) { |
517 | err = gk20a_channel_set_runlist_interleave(ce_ctx->ch, runlist_level); | 517 | err = gk20a_tsg_set_runlist_interleave(ce_ctx->tsg, |
518 | runlist_level); | ||
518 | if (err) { | 519 | if (err) { |
519 | nvgpu_err(g, | 520 | nvgpu_err(g, |
520 | "ce: could not set the runlist interleave for CE context"); | 521 | "ce: could not set the runlist interleave for CE context"); |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index f4a49a4b..aeac490a 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -129,16 +129,6 @@ int channel_gk20a_commit_va(struct channel_gk20a *c) | |||
129 | return 0; | 129 | return 0; |
130 | } | 130 | } |
131 | 131 | ||
132 | u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch) | ||
133 | { | ||
134 | struct gk20a *g = ch->g; | ||
135 | |||
136 | if (!ch->timeslice_us) | ||
137 | return g->ops.fifo.default_timeslice_us(g); | ||
138 | |||
139 | return ch->timeslice_us; | ||
140 | } | ||
141 | |||
142 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | 132 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, |
143 | int timeslice_period, | 133 | int timeslice_period, |
144 | int *__timeslice_timeout, int *__timeslice_scale) | 134 | int *__timeslice_timeout, int *__timeslice_scale) |
@@ -312,34 +302,6 @@ void gk20a_disable_channel(struct channel_gk20a *ch) | |||
312 | channel_gk20a_update_runlist(ch, false); | 302 | channel_gk20a_update_runlist(ch, false); |
313 | } | 303 | } |
314 | 304 | ||
315 | int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch, | ||
316 | u32 level) | ||
317 | { | ||
318 | struct gk20a *g = ch->g; | ||
319 | int ret; | ||
320 | |||
321 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
322 | nvgpu_err(g, "invalid operation for TSG!"); | ||
323 | return -EINVAL; | ||
324 | } | ||
325 | |||
326 | switch (level) { | ||
327 | case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW: | ||
328 | case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: | ||
329 | case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH: | ||
330 | ret = g->ops.fifo.set_runlist_interleave(g, ch->chid, | ||
331 | false, 0, level); | ||
332 | break; | ||
333 | default: | ||
334 | ret = -EINVAL; | ||
335 | break; | ||
336 | } | ||
337 | |||
338 | gk20a_dbg(gpu_dbg_sched, "chid=%u interleave=%u", ch->chid, level); | ||
339 | |||
340 | return ret ? ret : g->ops.fifo.update_runlist(g, ch->runlist_id, ~0, true, true); | ||
341 | } | ||
342 | |||
343 | static void gk20a_wait_until_counter_is_N( | 305 | static void gk20a_wait_until_counter_is_N( |
344 | struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value, | 306 | struct channel_gk20a *ch, nvgpu_atomic_t *counter, int wait_value, |
345 | struct nvgpu_cond *c, const char *caller, const char *counter_name) | 307 | struct nvgpu_cond *c, const char *caller, const char *counter_name) |
@@ -742,8 +704,6 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, | |||
742 | ch->has_timedout = false; | 704 | ch->has_timedout = false; |
743 | ch->wdt_enabled = true; | 705 | ch->wdt_enabled = true; |
744 | ch->obj_class = 0; | 706 | ch->obj_class = 0; |
745 | ch->interleave_level = NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW; | ||
746 | ch->timeslice_us = g->timeslice_low_priority_us; | ||
747 | #ifdef CONFIG_TEGRA_19x_GPU | 707 | #ifdef CONFIG_TEGRA_19x_GPU |
748 | memset(&ch->t19x, 0, sizeof(struct channel_t19x)); | 708 | memset(&ch->t19x, 0, sizeof(struct channel_t19x)); |
749 | #endif | 709 | #endif |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index b43c5638..596b85f3 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -247,7 +247,6 @@ struct channel_gk20a { | |||
247 | bool has_timedout; | 247 | bool has_timedout; |
248 | u32 timeout_ms_max; | 248 | u32 timeout_ms_max; |
249 | bool timeout_debug_dump; | 249 | bool timeout_debug_dump; |
250 | unsigned int timeslice_us; | ||
251 | 250 | ||
252 | struct nvgpu_mutex sync_lock; | 251 | struct nvgpu_mutex sync_lock; |
253 | struct gk20a_channel_sync *sync; | 252 | struct gk20a_channel_sync *sync; |
@@ -256,8 +255,6 @@ struct channel_gk20a { | |||
256 | u64 virt_ctx; | 255 | u64 virt_ctx; |
257 | #endif | 256 | #endif |
258 | 257 | ||
259 | u32 interleave_level; | ||
260 | |||
261 | u32 runlist_id; | 258 | u32 runlist_id; |
262 | 259 | ||
263 | bool is_privileged_channel; | 260 | bool is_privileged_channel; |
@@ -355,12 +352,9 @@ void channel_gk20a_joblist_unlock(struct channel_gk20a *c); | |||
355 | bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c); | 352 | bool channel_gk20a_joblist_is_empty(struct channel_gk20a *c); |
356 | 353 | ||
357 | int channel_gk20a_update_runlist(struct channel_gk20a *c, bool add); | 354 | int channel_gk20a_update_runlist(struct channel_gk20a *c, bool add); |
358 | u32 gk20a_channel_get_timeslice(struct channel_gk20a *ch); | ||
359 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | 355 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, |
360 | int timeslice_period, | 356 | int timeslice_period, |
361 | int *__timeslice_timeout, int *__timeslice_scale); | 357 | int *__timeslice_timeout, int *__timeslice_scale); |
362 | int gk20a_channel_set_runlist_interleave(struct channel_gk20a *ch, | ||
363 | u32 level); | ||
364 | 358 | ||
365 | int channel_gk20a_alloc_job(struct channel_gk20a *c, | 359 | int channel_gk20a_alloc_job(struct channel_gk20a *c, |
366 | struct channel_gk20a_job **job_out); | 360 | struct channel_gk20a_job **job_out); |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index fc71e907..194d5e3c 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -3075,48 +3075,11 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, | |||
3075 | bool last_level = cur_level == NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH; | 3075 | bool last_level = cur_level == NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH; |
3076 | struct channel_gk20a *ch; | 3076 | struct channel_gk20a *ch; |
3077 | bool skip_next = false; | 3077 | bool skip_next = false; |
3078 | u32 chid, tsgid, count = 0; | 3078 | u32 tsgid, count = 0; |
3079 | u32 runlist_entry_words = f->runlist_entry_size / sizeof(u32); | 3079 | u32 runlist_entry_words = f->runlist_entry_size / sizeof(u32); |
3080 | 3080 | ||
3081 | gk20a_dbg_fn(""); | 3081 | gk20a_dbg_fn(""); |
3082 | 3082 | ||
3083 | /* for each bare channel, CH, on this level, insert all higher-level | ||
3084 | channels and TSGs before inserting CH. */ | ||
3085 | for_each_set_bit(chid, runlist->active_channels, f->num_channels) { | ||
3086 | ch = &f->channel[chid]; | ||
3087 | |||
3088 | if (ch->interleave_level != cur_level) | ||
3089 | continue; | ||
3090 | |||
3091 | if (gk20a_is_channel_marked_as_tsg(ch)) | ||
3092 | continue; | ||
3093 | |||
3094 | if (!last_level && !skip_next) { | ||
3095 | runlist_entry = gk20a_runlist_construct_locked(f, | ||
3096 | runlist, | ||
3097 | cur_level + 1, | ||
3098 | runlist_entry, | ||
3099 | interleave_enabled, | ||
3100 | false, | ||
3101 | entries_left); | ||
3102 | /* if interleaving is disabled, higher-level channels | ||
3103 | and TSGs only need to be inserted once */ | ||
3104 | if (!interleave_enabled) | ||
3105 | skip_next = true; | ||
3106 | } | ||
3107 | |||
3108 | if (!(*entries_left)) | ||
3109 | return NULL; | ||
3110 | |||
3111 | gk20a_dbg_info("add channel %d to runlist", chid); | ||
3112 | f->g->ops.fifo.get_ch_runlist_entry(ch, runlist_entry); | ||
3113 | gk20a_dbg_info("run list count %d runlist [0] %x [1] %x\n", | ||
3114 | count, runlist_entry[0], runlist_entry[1]); | ||
3115 | runlist_entry += runlist_entry_words; | ||
3116 | count++; | ||
3117 | (*entries_left)--; | ||
3118 | } | ||
3119 | |||
3120 | /* for each TSG, T, on this level, insert all higher-level channels | 3083 | /* for each TSG, T, on this level, insert all higher-level channels |
3121 | and TSGs before inserting T. */ | 3084 | and TSGs before inserting T. */ |
3122 | for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) { | 3085 | for_each_set_bit(tsgid, runlist->active_tsgs, f->num_channels) { |
@@ -3204,16 +3167,12 @@ static u32 *gk20a_runlist_construct_locked(struct fifo_gk20a *f, | |||
3204 | 3167 | ||
3205 | int gk20a_fifo_set_runlist_interleave(struct gk20a *g, | 3168 | int gk20a_fifo_set_runlist_interleave(struct gk20a *g, |
3206 | u32 id, | 3169 | u32 id, |
3207 | bool is_tsg, | ||
3208 | u32 runlist_id, | 3170 | u32 runlist_id, |
3209 | u32 new_level) | 3171 | u32 new_level) |
3210 | { | 3172 | { |
3211 | gk20a_dbg_fn(""); | 3173 | gk20a_dbg_fn(""); |
3212 | 3174 | ||
3213 | if (is_tsg) | 3175 | g->fifo.tsg[id].interleave_level = new_level; |
3214 | g->fifo.tsg[id].interleave_level = new_level; | ||
3215 | else | ||
3216 | g->fifo.channel[id].interleave_level = new_level; | ||
3217 | 3176 | ||
3218 | return 0; | 3177 | return 0; |
3219 | } | 3178 | } |
@@ -3917,51 +3876,6 @@ int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, | |||
3917 | return gk20a_fifo_commit_userd(c); | 3876 | return gk20a_fifo_commit_userd(c); |
3918 | } | 3877 | } |
3919 | 3878 | ||
3920 | static int channel_gk20a_set_schedule_params(struct channel_gk20a *c) | ||
3921 | { | ||
3922 | int shift = 0, value = 0; | ||
3923 | |||
3924 | gk20a_channel_get_timescale_from_timeslice(c->g, | ||
3925 | c->timeslice_us, &value, &shift); | ||
3926 | |||
3927 | /* disable channel */ | ||
3928 | c->g->ops.fifo.disable_channel(c); | ||
3929 | |||
3930 | /* preempt the channel */ | ||
3931 | WARN_ON(c->g->ops.fifo.preempt_channel(c->g, c->chid)); | ||
3932 | |||
3933 | /* set new timeslice */ | ||
3934 | nvgpu_mem_wr32(c->g, &c->inst_block, ram_fc_runlist_timeslice_w(), | ||
3935 | value | (shift << 12) | | ||
3936 | fifo_runlist_timeslice_enable_true_f()); | ||
3937 | |||
3938 | /* enable channel */ | ||
3939 | c->g->ops.fifo.enable_channel(c); | ||
3940 | |||
3941 | return 0; | ||
3942 | } | ||
3943 | |||
3944 | int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, u32 timeslice) | ||
3945 | { | ||
3946 | struct gk20a *g = ch->g; | ||
3947 | |||
3948 | if (gk20a_is_channel_marked_as_tsg(ch)) { | ||
3949 | nvgpu_err(g, "invalid operation for TSG!"); | ||
3950 | return -EINVAL; | ||
3951 | } | ||
3952 | |||
3953 | if (timeslice < g->min_timeslice_us || | ||
3954 | timeslice > g->max_timeslice_us) | ||
3955 | return -EINVAL; | ||
3956 | |||
3957 | ch->timeslice_us = timeslice; | ||
3958 | |||
3959 | gk20a_dbg(gpu_dbg_sched, "chid=%u timeslice=%u us", | ||
3960 | ch->chid, timeslice); | ||
3961 | |||
3962 | return channel_gk20a_set_schedule_params(ch); | ||
3963 | } | ||
3964 | |||
3965 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) | 3879 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c) |
3966 | { | 3880 | { |
3967 | struct gk20a *g = c->g; | 3881 | struct gk20a *g = c->g; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 3587ffa8..7fdd3b6b 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -297,12 +297,10 @@ struct channel_gk20a *gk20a_fifo_channel_from_chid(struct gk20a *g, | |||
297 | void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg); | 297 | void gk20a_fifo_issue_preempt(struct gk20a *g, u32 id, bool is_tsg); |
298 | int gk20a_fifo_set_runlist_interleave(struct gk20a *g, | 298 | int gk20a_fifo_set_runlist_interleave(struct gk20a *g, |
299 | u32 id, | 299 | u32 id, |
300 | bool is_tsg, | ||
301 | u32 runlist_id, | 300 | u32 runlist_id, |
302 | u32 new_level); | 301 | u32 new_level); |
303 | int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); | 302 | int gk20a_fifo_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); |
304 | 303 | ||
305 | |||
306 | const char *gk20a_fifo_interleave_level_name(u32 interleave_level); | 304 | const char *gk20a_fifo_interleave_level_name(u32 interleave_level); |
307 | 305 | ||
308 | int gk20a_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, | 306 | int gk20a_fifo_engine_enum_from_type(struct gk20a *g, u32 engine_type, |
@@ -383,7 +381,6 @@ void __locked_fifo_preempt_timeout_rc(struct gk20a *g, u32 id, | |||
383 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, | 381 | int gk20a_fifo_setup_ramfc(struct channel_gk20a *c, |
384 | u64 gpfifo_base, u32 gpfifo_entries, | 382 | u64 gpfifo_base, u32 gpfifo_entries, |
385 | unsigned long timeout, u32 flags); | 383 | unsigned long timeout, u32 flags); |
386 | int gk20a_fifo_set_timeslice(struct channel_gk20a *ch, unsigned int timeslice); | ||
387 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); | 384 | void gk20a_fifo_setup_ramfc_for_privileged_channel(struct channel_gk20a *c); |
388 | int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); | 385 | int gk20a_fifo_alloc_inst(struct gk20a *g, struct channel_gk20a *ch); |
389 | void gk20a_fifo_free_inst(struct gk20a *g, struct channel_gk20a *ch); | 386 | void gk20a_fifo_free_inst(struct gk20a *g, struct channel_gk20a *ch); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ebe29bc3..6a669d88 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -535,10 +535,8 @@ struct gpu_ops { | |||
535 | u32 (*get_num_fifos)(struct gk20a *g); | 535 | u32 (*get_num_fifos)(struct gk20a *g); |
536 | u32 (*get_pbdma_signature)(struct gk20a *g); | 536 | u32 (*get_pbdma_signature)(struct gk20a *g); |
537 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, | 537 | int (*set_runlist_interleave)(struct gk20a *g, u32 id, |
538 | bool is_tsg, u32 runlist_id, | 538 | u32 runlist_id, |
539 | u32 new_level); | 539 | u32 new_level); |
540 | int (*channel_set_timeslice)(struct channel_gk20a *ch, | ||
541 | u32 timeslice); | ||
542 | int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); | 540 | int (*tsg_set_timeslice)(struct tsg_gk20a *tsg, u32 timeslice); |
543 | u32 (*default_timeslice_us)(struct gk20a *); | 541 | u32 (*default_timeslice_us)(struct gk20a *); |
544 | int (*force_reset_ch)(struct channel_gk20a *ch, | 542 | int (*force_reset_ch)(struct channel_gk20a *ch, |
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 64d521a0..ff700372 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -211,7 +211,7 @@ int gk20a_tsg_set_runlist_interleave(struct tsg_gk20a *tsg, u32 level) | |||
211 | case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: | 211 | case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_MEDIUM: |
212 | case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH: | 212 | case NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_HIGH: |
213 | ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid, | 213 | ret = g->ops.fifo.set_runlist_interleave(g, tsg->tsgid, |
214 | true, 0, level); | 214 | 0, level); |
215 | if (!ret) | 215 | if (!ret) |
216 | tsg->interleave_level = level; | 216 | tsg->interleave_level = level; |
217 | break; | 217 | break; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index d89ff2fe..c29f7267 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -387,7 +387,6 @@ static const struct gpu_ops gm20b_ops = { | |||
387 | .alloc_inst = gk20a_fifo_alloc_inst, | 387 | .alloc_inst = gk20a_fifo_alloc_inst, |
388 | .free_inst = gk20a_fifo_free_inst, | 388 | .free_inst = gk20a_fifo_free_inst, |
389 | .setup_ramfc = gk20a_fifo_setup_ramfc, | 389 | .setup_ramfc = gk20a_fifo_setup_ramfc, |
390 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
391 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 390 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
392 | .setup_userd = gk20a_fifo_setup_userd, | 391 | .setup_userd = gk20a_fifo_setup_userd, |
393 | .userd_gp_get = gk20a_fifo_userd_gp_get, | 392 | .userd_gp_get = gk20a_fifo_userd_gp_get, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 2150b1ec..9052b4b2 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -442,7 +442,6 @@ static const struct gpu_ops gp106_ops = { | |||
442 | .alloc_inst = gk20a_fifo_alloc_inst, | 442 | .alloc_inst = gk20a_fifo_alloc_inst, |
443 | .free_inst = gk20a_fifo_free_inst, | 443 | .free_inst = gk20a_fifo_free_inst, |
444 | .setup_ramfc = channel_gp10b_setup_ramfc, | 444 | .setup_ramfc = channel_gp10b_setup_ramfc, |
445 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
446 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 445 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
447 | .setup_userd = gk20a_fifo_setup_userd, | 446 | .setup_userd = gk20a_fifo_setup_userd, |
448 | .userd_gp_get = gk20a_fifo_userd_gp_get, | 447 | .userd_gp_get = gk20a_fifo_userd_gp_get, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 06311347..5e8e7acc 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -414,7 +414,6 @@ static const struct gpu_ops gp10b_ops = { | |||
414 | .alloc_inst = gk20a_fifo_alloc_inst, | 414 | .alloc_inst = gk20a_fifo_alloc_inst, |
415 | .free_inst = gk20a_fifo_free_inst, | 415 | .free_inst = gk20a_fifo_free_inst, |
416 | .setup_ramfc = channel_gp10b_setup_ramfc, | 416 | .setup_ramfc = channel_gp10b_setup_ramfc, |
417 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
418 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 417 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
419 | .setup_userd = gk20a_fifo_setup_userd, | 418 | .setup_userd = gk20a_fifo_setup_userd, |
420 | .userd_gp_get = gk20a_fifo_userd_gp_get, | 419 | .userd_gp_get = gk20a_fifo_userd_gp_get, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index a09d8912..d2136466 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -450,7 +450,6 @@ static const struct gpu_ops gv100_ops = { | |||
450 | .alloc_inst = gk20a_fifo_alloc_inst, | 450 | .alloc_inst = gk20a_fifo_alloc_inst, |
451 | .free_inst = gk20a_fifo_free_inst, | 451 | .free_inst = gk20a_fifo_free_inst, |
452 | .setup_ramfc = channel_gv11b_setup_ramfc, | 452 | .setup_ramfc = channel_gv11b_setup_ramfc, |
453 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
454 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 453 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
455 | .setup_userd = gk20a_fifo_setup_userd, | 454 | .setup_userd = gk20a_fifo_setup_userd, |
456 | .userd_gp_get = gv11b_userd_gp_get, | 455 | .userd_gp_get = gv11b_userd_gp_get, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 83bd7612..ff26f694 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -474,7 +474,6 @@ static const struct gpu_ops gv11b_ops = { | |||
474 | .alloc_inst = gk20a_fifo_alloc_inst, | 474 | .alloc_inst = gk20a_fifo_alloc_inst, |
475 | .free_inst = gk20a_fifo_free_inst, | 475 | .free_inst = gk20a_fifo_free_inst, |
476 | .setup_ramfc = channel_gv11b_setup_ramfc, | 476 | .setup_ramfc = channel_gv11b_setup_ramfc, |
477 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
478 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | 477 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, |
479 | .setup_userd = gk20a_fifo_setup_userd, | 478 | .setup_userd = gk20a_fifo_setup_userd, |
480 | .userd_gp_get = gv11b_userd_gp_get, | 479 | .userd_gp_get = gv11b_userd_gp_get, |