gpu: nvgpu: determine memory configuration in hal

Remove mem_config_idx from platform data, and instead let
HAL determine which memory configuration to use. For this
purpose, HAL may use PCI device identifiers, VBIOS version
and possibly RAMCFG strap register.

Bug 1929155

Change-Id: I6633e9e0c79728c8e3740f3f956b53b3abfc667b
Reviewed-on: http://git-master/r/1497812
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
(cherry picked from commit b7141ff5441b7ea95f9826eb37ae869f408e1414)
Reviewed-on: https://git-master/r/1506584
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
index 56f1e194..632023ba 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c
@@ -332,6 +332,7 @@ void gp106_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.pmu_pg_param_post_init = nvgpu_lpwr_post_init;
         gops->pmu.dump_secure_fuses = NULL;
         gops->pmu.mclk_init = gp106_mclk_init;
+        gops->pmu.mclk_change = gp106_mclk_change;
         gops->pmu.mclk_deinit = gp106_mclk_deinit;
         gops->pmu.is_pmu_supported = gp106_is_pmu_supported;
         gops->pmu.reset_engine = gp106_pmu_engine_reset;
diff --git a/drivers/gpu/nvgpu/gp106/pmu_mclk_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_mclk_gp106.c
index c510a8d7..2ca29750 100644
--- a/drivers/gpu/nvgpu/gp106/pmu_mclk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/pmu_mclk_gp106.c
@@ -2725,6 +2725,14 @@ int gp106_mclk_init(struct gk20a *g)
 
         mclk->speed = GP106_MCLK_LOW_SPEED; /* Value from Devinit */
 
+        /* Find out which memory configuration to use */
+        g->mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG418;
+        if ((g->pci_vendor_id == PCI_VENDOR_ID_NVIDIA) &&
+                (g->pci_device_id == 0x1c75) &&
+                (g->gpu_characteristics.vbios_version == 0x86065800)) {
+                g->mem_config_idx = GP106_MEM_CONFIG_GDDR5_PG419;
+        }
+
         /* Parse VBIOS */
         status = mclk_get_memclk_table(g);
         if (status < 0) {
@@ -2791,6 +2799,7 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
         u32 seqdesc;
         int status = 0;
         struct memory_config *m = &mem_config[g->mem_config_idx];
+
         u32 seq_completion_status = ~0x0;
         u8 *seq_script_ptr = NULL;
         size_t seq_script_size = 0;