diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-10-23 16:27:28 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-01 18:26:28 -0400 |
commit | 7e59e0b09b605c4082fb812fb0842537819282cf (patch) | |
tree | 2b3e76db071626e8dcc51b14d39d5e610dacbb2c /drivers | |
parent | 5d260a24a526c35e42ed9f0bd90ba30b8dd19a60 (diff) |
gpu: nvgpu: save act_eng_bitmask in runlist_info
Issue
Currently bitmask of engine indices is being saved.
This will give wrong active engine ids for a given runlist
and s/w will end up checking/polling wrong engine_status
registers as these registers are indexed by active
engine ids. Also reset_eng_bitmask will end up
having wrong value for active engine ids to be reset.
Details for runlists serving engines ids for gv11b are:-
runlist id 0: gr = 0, grcopy 0 = 2, grcopy1 = 3
runlist id 1: async ce = 1
Incorrect values
init_runlist:705 [DBG] runlist 0 : eng bitmask 7 (eng 0, 1, 2)
init_runlist:705 [DBG] runlist 1 : eng bitmask 8 (eng 3)
Fix
Save bitmask of active engine ids in runlist info.
Right value
init_runlist:705 [DBG] runlist 0 : eng bitmask d (eng 0, 2, 3)
init_runlist:705 [DBG] runlist 1 : eng bitmask 2 (eng 1)
Bug 200277163
Bug 1945121
Change-Id: Ia299aa0881c4a258080bb0daa3a542fef0d94e4f
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584066
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 5d04aa0c..f3ed2efb 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -662,7 +662,7 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | |||
662 | u32 active_engine_id, pbdma_id, engine_id; | 662 | u32 active_engine_id, pbdma_id, engine_id; |
663 | struct fifo_engine_info_gk20a *engine_info; | 663 | struct fifo_engine_info_gk20a *engine_info; |
664 | 664 | ||
665 | gk20a_dbg_fn(""); | 665 | nvgpu_log_fn(g, " "); |
666 | 666 | ||
667 | f->max_runlists = g->ops.fifo.eng_runlist_base_size(); | 667 | f->max_runlists = g->ops.fifo.eng_runlist_base_size(); |
668 | f->runlist_info = nvgpu_kzalloc(g, | 668 | f->runlist_info = nvgpu_kzalloc(g, |
@@ -690,8 +690,9 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | |||
690 | goto clean_up_runlist; | 690 | goto clean_up_runlist; |
691 | 691 | ||
692 | runlist_size = f->runlist_entry_size * f->num_runlist_entries; | 692 | runlist_size = f->runlist_entry_size * f->num_runlist_entries; |
693 | gk20a_dbg_info("runlist_entries %d runlist size %zu\n", | 693 | nvgpu_log(g, gpu_dbg_info, |
694 | f->num_runlist_entries, runlist_size); | 694 | "runlist_entries %d runlist size %zu", |
695 | f->num_runlist_entries, runlist_size); | ||
695 | 696 | ||
696 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { | 697 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { |
697 | int err = nvgpu_dma_alloc_sys(g, runlist_size, | 698 | int err = nvgpu_dma_alloc_sys(g, runlist_size, |
@@ -711,7 +712,7 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | |||
711 | if (f->pbdma_map[pbdma_id] & BIT(runlist_id)) | 712 | if (f->pbdma_map[pbdma_id] & BIT(runlist_id)) |
712 | runlist->pbdma_bitmask |= BIT(pbdma_id); | 713 | runlist->pbdma_bitmask |= BIT(pbdma_id); |
713 | } | 714 | } |
714 | gk20a_dbg_info("runlist %d : pbdma bitmask %x", | 715 | nvgpu_log(g, gpu_dbg_info, "runlist %d : pbdma bitmask 0x%x", |
715 | runlist_id, runlist->pbdma_bitmask); | 716 | runlist_id, runlist->pbdma_bitmask); |
716 | 717 | ||
717 | for (engine_id = 0; engine_id < f->num_engines; ++engine_id) { | 718 | for (engine_id = 0; engine_id < f->num_engines; ++engine_id) { |
@@ -719,14 +720,13 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | |||
719 | engine_info = &f->engine_info[active_engine_id]; | 720 | engine_info = &f->engine_info[active_engine_id]; |
720 | 721 | ||
721 | if (engine_info && engine_info->runlist_id == runlist_id) | 722 | if (engine_info && engine_info->runlist_id == runlist_id) |
722 | runlist->eng_bitmask |= BIT(engine_id); | 723 | runlist->eng_bitmask |= BIT(active_engine_id); |
723 | } | 724 | } |
724 | gk20a_dbg_info("runlist %d : eng bitmask %x", | 725 | nvgpu_log(g, gpu_dbg_info, "runlist %d : act eng bitmask 0x%x", |
725 | runlist_id, runlist->eng_bitmask); | 726 | runlist_id, runlist->eng_bitmask); |
726 | } | 727 | } |
727 | 728 | ||
728 | 729 | nvgpu_log_fn(g, "done"); | |
729 | gk20a_dbg_fn("done"); | ||
730 | return 0; | 730 | return 0; |
731 | 731 | ||
732 | clean_up_runlist: | 732 | clean_up_runlist: |