diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-07-05 06:42:29 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-06 02:25:27 -0400 |
commit | 79a79b8ae6987e5620c9bc7ee080fe637a6ca57b (patch) | |
tree | 5e482d8d1a584e9496b2daa880adfd00b5f65ecb /drivers | |
parent | 3afac13d66ee7026555c0b0558d898a4f189b051 (diff) |
gpu: nvgpu: falcon bootstrap support
- Added falcon interface/HAL to bootstrap
falcon by taking boot vector as parameter
- Replaced falcon bootstrap code in multiple
files with nvgpu_flcn_bootstrap() method
JIRA NVGPU-102
Change-Id: I4324824c50c6196d8b7ecf981f815ec778da2fd9
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1513643
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/falcon/falcon.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/bios_gm206.c | 14 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/sec2_gp106.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/falcon.h | 2 |
7 files changed, 44 insertions, 30 deletions
diff --git a/drivers/gpu/nvgpu/common/falcon/falcon.c b/drivers/gpu/nvgpu/common/falcon/falcon.c index 74d78e86..4c879e52 100644 --- a/drivers/gpu/nvgpu/common/falcon/falcon.c +++ b/drivers/gpu/nvgpu/common/falcon/falcon.c | |||
@@ -196,6 +196,20 @@ int nvgpu_flcn_copy_to_imem(struct nvgpu_falcon *flcn, | |||
196 | return status; | 196 | return status; |
197 | } | 197 | } |
198 | 198 | ||
199 | int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector) | ||
200 | { | ||
201 | struct nvgpu_falcon_ops *flcn_ops = &flcn->flcn_ops; | ||
202 | int status = -EINVAL; | ||
203 | |||
204 | if (flcn_ops->bootstrap) | ||
205 | status = flcn_ops->bootstrap(flcn, boot_vector); | ||
206 | else | ||
207 | nvgpu_warn(flcn->g, "Invalid op on falcon 0x%x ", | ||
208 | flcn->flcn_id); | ||
209 | |||
210 | return status; | ||
211 | } | ||
212 | |||
199 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) | 213 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id) |
200 | { | 214 | { |
201 | struct nvgpu_falcon *flcn = NULL; | 215 | struct nvgpu_falcon *flcn = NULL; |
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c index 158f4d8b..0ef10a56 100644 --- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c | |||
@@ -324,6 +324,26 @@ static int gk20a_flcn_copy_to_imem(struct nvgpu_falcon *flcn, u32 dst, | |||
324 | return 0; | 324 | return 0; |
325 | } | 325 | } |
326 | 326 | ||
327 | static int gk20a_falcon_bootstrap(struct nvgpu_falcon *flcn, | ||
328 | u32 boot_vector) | ||
329 | { | ||
330 | struct gk20a *g = flcn->g; | ||
331 | u32 base_addr = flcn->flcn_base; | ||
332 | |||
333 | nvgpu_log_info(g, "boot vec 0x%x", boot_vector); | ||
334 | |||
335 | gk20a_writel(g, base_addr + falcon_falcon_dmactl_r(), | ||
336 | falcon_falcon_dmactl_require_ctx_f(0)); | ||
337 | |||
338 | gk20a_writel(g, base_addr + falcon_falcon_bootvec_r(), | ||
339 | falcon_falcon_bootvec_vec_f(boot_vector)); | ||
340 | |||
341 | gk20a_writel(g, base_addr + falcon_falcon_cpuctl_r(), | ||
342 | falcon_falcon_cpuctl_startcpu_f(1)); | ||
343 | |||
344 | return 0; | ||
345 | } | ||
346 | |||
327 | static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) | 347 | static void gk20a_falcon_engine_dependency_ops(struct nvgpu_falcon *flcn) |
328 | { | 348 | { |
329 | struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = | 349 | struct nvgpu_falcon_engine_dependency_ops *flcn_eng_dep_ops = |
@@ -357,6 +377,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn) | |||
357 | flcn_ops->copy_from_dmem = gk20a_flcn_copy_from_dmem; | 377 | flcn_ops->copy_from_dmem = gk20a_flcn_copy_from_dmem; |
358 | flcn_ops->copy_to_dmem = gk20a_flcn_copy_to_dmem; | 378 | flcn_ops->copy_to_dmem = gk20a_flcn_copy_to_dmem; |
359 | flcn_ops->copy_to_imem = gk20a_flcn_copy_to_imem; | 379 | flcn_ops->copy_to_imem = gk20a_flcn_copy_to_imem; |
380 | flcn_ops->bootstrap = gk20a_falcon_bootstrap; | ||
360 | 381 | ||
361 | gk20a_falcon_engine_dependency_ops(flcn); | 382 | gk20a_falcon_engine_dependency_ops(flcn); |
362 | } | 383 | } |
@@ -396,7 +417,7 @@ static void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn) | |||
396 | nvgpu_mutex_init(&flcn->copy_lock); | 417 | nvgpu_mutex_init(&flcn->copy_lock); |
397 | gk20a_falcon_ops(flcn); | 418 | gk20a_falcon_ops(flcn); |
398 | } else | 419 | } else |
399 | nvgpu_info(g, "falcon 0x%x not supported on %s", | 420 | nvgpu_log_info(g, "falcon 0x%x not supported on %s", |
400 | flcn->flcn_id, g->name); | 421 | flcn->flcn_id, g->name); |
401 | } | 422 | } |
402 | 423 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index b3cacb86..7cf8c475 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -23,6 +23,7 @@ | |||
23 | #include <nvgpu/log.h> | 23 | #include <nvgpu/log.h> |
24 | #include <nvgpu/bug.h> | 24 | #include <nvgpu/bug.h> |
25 | #include <nvgpu/firmware.h> | 25 | #include <nvgpu/firmware.h> |
26 | #include <nvgpu/falcon.h> | ||
26 | 27 | ||
27 | #include "gk20a.h" | 28 | #include "gk20a.h" |
28 | #include "gr_gk20a.h" | 29 | #include "gr_gk20a.h" |
@@ -239,11 +240,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu) | |||
239 | pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); | 240 | pwr_falcon_dmatrfcmd_ctxdma_f(GK20A_PMU_DMAIDX_UCODE)); |
240 | } | 241 | } |
241 | 242 | ||
242 | gk20a_writel(g, pwr_falcon_bootvec_r(), | 243 | nvgpu_flcn_bootstrap(g->pmu.flcn, desc->bootloader_entry_point); |
243 | pwr_falcon_bootvec_vec_f(desc->bootloader_entry_point)); | ||
244 | |||
245 | gk20a_writel(g, pwr_falcon_cpuctl_r(), | ||
246 | pwr_falcon_cpuctl_startcpu_f(1)); | ||
247 | 244 | ||
248 | gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); | 245 | gk20a_writel(g, pwr_falcon_os_r(), desc->app_version); |
249 | 246 | ||
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index 14610120..13f5023a 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c | |||
@@ -101,12 +101,7 @@ static int gm206_bios_devinit(struct gk20a *g) | |||
101 | g->bios.bootscripts_size, | 101 | g->bios.bootscripts_size, |
102 | 0); | 102 | 0); |
103 | 103 | ||
104 | gk20a_writel(g, pwr_falcon_bootvec_r(), | 104 | nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.devinit.code_entry_point); |
105 | pwr_falcon_bootvec_vec_f(g->bios.devinit.code_entry_point)); | ||
106 | gk20a_writel(g, pwr_falcon_dmactl_r(), | ||
107 | pwr_falcon_dmactl_require_ctx_f(0)); | ||
108 | gk20a_writel(g, pwr_falcon_cpuctl_r(), | ||
109 | pwr_falcon_cpuctl_startcpu_f(1)); | ||
110 | 105 | ||
111 | nvgpu_timeout_init(g, &timeout, | 106 | nvgpu_timeout_init(g, &timeout, |
112 | PMU_BOOT_TIMEOUT_MAX / | 107 | PMU_BOOT_TIMEOUT_MAX / |
@@ -155,12 +150,7 @@ static int gm206_bios_preos(struct gk20a *g) | |||
155 | g->bios.preos.dmem_size, | 150 | g->bios.preos.dmem_size, |
156 | 0); | 151 | 0); |
157 | 152 | ||
158 | gk20a_writel(g, pwr_falcon_bootvec_r(), | 153 | nvgpu_flcn_bootstrap(g->pmu.flcn, g->bios.preos.code_entry_point); |
159 | pwr_falcon_bootvec_vec_f(g->bios.preos.code_entry_point)); | ||
160 | gk20a_writel(g, pwr_falcon_dmactl_r(), | ||
161 | pwr_falcon_dmactl_require_ctx_f(0)); | ||
162 | gk20a_writel(g, pwr_falcon_cpuctl_r(), | ||
163 | pwr_falcon_cpuctl_startcpu_f(1)); | ||
164 | 154 | ||
165 | if (nvgpu_flcn_wait_for_halt(g->pmu.flcn, | 155 | if (nvgpu_flcn_wait_for_halt(g->pmu.flcn, |
166 | PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT)) { | 156 | PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT)) { |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 3a638373..1bc51a7c 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1251,11 +1251,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
1251 | gm20b_dbg_pmu("Before starting falcon with BL\n"); | 1251 | gm20b_dbg_pmu("Before starting falcon with BL\n"); |
1252 | 1252 | ||
1253 | virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; | 1253 | virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; |
1254 | gk20a_writel(g, pwr_falcon_bootvec_r(), | ||
1255 | pwr_falcon_bootvec_vec_f(virt_addr)); | ||
1256 | 1254 | ||
1257 | gk20a_writel(g, pwr_falcon_cpuctl_r(), | 1255 | nvgpu_flcn_bootstrap(pmu->flcn, virt_addr); |
1258 | pwr_falcon_cpuctl_startcpu_f(1)); | ||
1259 | 1256 | ||
1260 | return 0; | 1257 | return 0; |
1261 | } | 1258 | } |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index ccd1b3ad..f5e7f2be 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -110,11 +110,8 @@ int bl_bootstrap_sec2(struct nvgpu_pmu *pmu, | |||
110 | gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5); | 110 | gk20a_writel(g, psec_falcon_mailbox0_r(), 0xDEADA5A5); |
111 | 111 | ||
112 | virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; | 112 | virt_addr = pmu_bl_gm10x_desc->bl_start_tag << 8; |
113 | gk20a_writel(g, psec_falcon_bootvec_r(), | ||
114 | psec_falcon_bootvec_vec_f(virt_addr)); | ||
115 | 113 | ||
116 | gk20a_writel(g, psec_falcon_cpuctl_r(), | 114 | nvgpu_flcn_bootstrap(&g->sec2_flcn, virt_addr); |
117 | psec_falcon_cpuctl_startcpu_f(1)); | ||
118 | 115 | ||
119 | return 0; | 116 | return 0; |
120 | } | 117 | } |
@@ -198,10 +195,6 @@ int init_sec2_setup_hw1(struct gk20a *g, | |||
198 | data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f(); | 195 | data |= psec_fbif_ctl_allow_phys_no_ctx_allow_f(); |
199 | gk20a_writel(g, psec_fbif_ctl_r(), data); | 196 | gk20a_writel(g, psec_fbif_ctl_r(), data); |
200 | 197 | ||
201 | data = gk20a_readl(g, psec_falcon_dmactl_r()); | ||
202 | data &= ~(psec_falcon_dmactl_require_ctx_f(1)); | ||
203 | gk20a_writel(g, psec_falcon_dmactl_r(), data); | ||
204 | |||
205 | /* setup apertures - virtual */ | 198 | /* setup apertures - virtual */ |
206 | gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | 199 | gk20a_writel(g, psec_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), |
207 | psec_fbif_transcfg_mem_type_physical_f() | | 200 | psec_fbif_transcfg_mem_type_physical_f() | |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/falcon.h b/drivers/gpu/nvgpu/include/nvgpu/falcon.h index 36e9ffb1..cbda2ee3 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/falcon.h +++ b/drivers/gpu/nvgpu/include/nvgpu/falcon.h | |||
@@ -146,6 +146,7 @@ struct nvgpu_falcon_ops { | |||
146 | u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index); | 146 | u32 (*mailbox_read)(struct nvgpu_falcon *flcn, u32 mailbox_index); |
147 | void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index, | 147 | void (*mailbox_write)(struct nvgpu_falcon *flcn, u32 mailbox_index, |
148 | u32 data); | 148 | u32 data); |
149 | int (*bootstrap)(struct nvgpu_falcon *flcn, u32 boot_vector); | ||
149 | void (*dump_falcon_stats)(struct nvgpu_falcon *flcn); | 150 | void (*dump_falcon_stats)(struct nvgpu_falcon *flcn); |
150 | }; | 151 | }; |
151 | 152 | ||
@@ -187,6 +188,7 @@ int nvgpu_flcn_dma_copy(struct nvgpu_falcon *flcn, | |||
187 | u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); | 188 | u32 nvgpu_flcn_mailbox_read(struct nvgpu_falcon *flcn, u32 mailbox_index); |
188 | void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, | 189 | void nvgpu_flcn_mailbox_write(struct nvgpu_falcon *flcn, u32 mailbox_index, |
189 | u32 data); | 190 | u32 data); |
191 | int nvgpu_flcn_bootstrap(struct nvgpu_falcon *flcn, u32 boot_vector); | ||
190 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); | 192 | void nvgpu_flcn_dump_stats(struct nvgpu_falcon *flcn); |
191 | 193 | ||
192 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); | 194 | void nvgpu_flcn_sw_init(struct gk20a *g, u32 flcn_id); |