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authorTerje Bergstrom <tbergstrom@nvidia.com>2014-09-10 07:32:08 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:23 -0400
commit78c46b85556ca1cf0fd15d504a309f9c508064e6 (patch)
tree47b5873f2c234aec905b3c0c5d95992b5fcf5e05 /drivers
parent9981cf44243e644e7ba3f01b66e08bea5b24979b (diff)
gpu: nvgpu: gm20b: Fix build warnings
Fix build warnings by removing the unused variables, functions and duplicated code. Enable -Werror to prevent new build warnings. Change-Id: Ifd73344a6e12497e6dca595ac7a6edd7ca698f88 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/497374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gm20b/Makefile1
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.c6
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c12
-rw-r--r--drivers/gpu/nvgpu/gm20b/ltc_gm20b.c3
-rw-r--r--drivers/gpu/nvgpu/gm20b/mm_gm20b.c50
5 files changed, 8 insertions, 64 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/Makefile b/drivers/gpu/nvgpu/gm20b/Makefile
index 772f3997..154fdcd5 100644
--- a/drivers/gpu/nvgpu/gm20b/Makefile
+++ b/drivers/gpu/nvgpu/gm20b/Makefile
@@ -1,6 +1,7 @@
1GCOV_PROFILE := y 1GCOV_PROFILE := y
2ccflags-y += -Idrivers/gpu/nvgpu 2ccflags-y += -Idrivers/gpu/nvgpu
3ccflags-y += -Wno-multichar 3ccflags-y += -Wno-multichar
4ccflags-y += -Werror
4 5
5obj-$(CONFIG_GK20A) = \ 6obj-$(CONFIG_GK20A) = \
6 hal_gm20b.o \ 7 hal_gm20b.o \
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 3df2f9c5..7e70d5a4 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -838,8 +838,8 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g)
838 int i, err = 0; 838 int i, err = 0;
839 struct sg_table *sgt_pmu_ucode = NULL; 839 struct sg_table *sgt_pmu_ucode = NULL;
840 dma_addr_t iova; 840 dma_addr_t iova;
841 u64 *pacr_ucode_cpuva = NULL, pacr_ucode_pmu_va, *acr_dmem; 841 u64 *pacr_ucode_cpuva = NULL, pacr_ucode_pmu_va = 0, *acr_dmem;
842 u32 img_size_in_bytes; 842 u32 img_size_in_bytes = 0;
843 u32 status, size; 843 u32 status, size;
844 u64 start; 844 u64 start;
845 struct acr_gm20b *acr = &g->acr; 845 struct acr_gm20b *acr = &g->acr;
@@ -980,9 +980,7 @@ err_release_acr_fw:
980 980
981u8 pmu_is_debug_mode_en(struct gk20a *g) 981u8 pmu_is_debug_mode_en(struct gk20a *g)
982{ 982{
983 int ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r());
984 return 1; 983 return 1;
985 /*TODO return (ctl_stat & pwr_pmu_scpctl_stat_debug_mode_m());*/
986} 984}
987 985
988/* 986/*
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 7949405c..6bf0ed27 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -497,7 +497,7 @@ static int gr_gm20b_ctx_state_floorsweep(struct gk20a *g)
497 u32 sm_id = 0, gpc_id = 0; 497 u32 sm_id = 0, gpc_id = 0;
498 u32 sm_id_to_gpc_id[proj_scal_max_gpcs_v() * proj_scal_max_tpc_per_gpc_v()]; 498 u32 sm_id_to_gpc_id[proj_scal_max_gpcs_v() * proj_scal_max_tpc_per_gpc_v()];
499 u32 tpc_per_gpc; 499 u32 tpc_per_gpc;
500 u32 tpc_fs_mask = 0, tpc_sm_id, gpc_tpc_id; 500 u32 tpc_fs_mask = 0, tpc_sm_id = 0, gpc_tpc_id = 0;
501 501
502 gk20a_dbg_fn(""); 502 gk20a_dbg_fn("");
503 503
@@ -689,10 +689,6 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
689 689
690static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) 690static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
691{ 691{
692 struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info;
693 u64 addr_base = ucode_info->ucode_gpuva;
694 int i;
695
696 gk20a_dbg_fn(""); 692 gk20a_dbg_fn("");
697 693
698 if (tegra_platform_is_linsim()) { 694 if (tegra_platform_is_linsim()) {
@@ -702,11 +698,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
702 gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777)); 698 gr_gpccs_ctxsw_mailbox_value_f(0xc0de7777));
703 } 699 }
704 700
705 gr_gk20a_load_falcon_bind_instblk(g); 701 gr_gm20b_load_gpccs_with_bootloader(g);
706 g->ops.gr.falcon_load_ucode(g, addr_base,
707 &g->ctxsw_ucode_info.gpccs,
708 gr_gpcs_gpccs_falcon_hwcfg_r() -
709 gr_fecs_falcon_hwcfg_r());
710 702
711 gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0x0); 703 gk20a_writel(g, gr_fecs_ctxsw_mailbox_clear_r(0), 0x0);
712 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1); 704 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(1), 0x1);
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index 6e9d6ffe..96e5dbde 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -364,4 +364,7 @@ void gm20b_init_ltc(struct gpu_ops *gops)
364 gops->ltc.isr = gm20b_ltc_isr; 364 gops->ltc.isr = gm20b_ltc_isr;
365 gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; 365 gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config;
366 gops->ltc.flush = gm20b_flush_ltc; 366 gops->ltc.flush = gm20b_flush_ltc;
367#ifdef CONFIG_DEBUG_FS
368 gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs;
369#endif
367} 370}
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index afb04cae..278ae9a6 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -90,52 +90,6 @@ fail:
90 90
91} 91}
92 92
93static void allocate_gmmu_pde_sparse(struct vm_gk20a *vm, u32 i)
94{
95 bool small_valid, big_valid;
96 u64 pte_addr[2] = {0, 0};
97 struct page_table_gk20a *small_pte =
98 vm->pdes.ptes[gmmu_page_size_small] + i;
99 struct page_table_gk20a *big_pte =
100 vm->pdes.ptes[gmmu_page_size_big] + i;
101 u32 pde_v[2] = {0, 0};
102 u32 *pde;
103
104 gk20a_dbg_fn("");
105
106 small_valid = small_pte && small_pte->ref;
107 big_valid = big_pte && big_pte->ref;
108
109 if (small_valid)
110 pte_addr[gmmu_page_size_small] =
111 gk20a_mm_iova_addr(small_pte->sgt->sgl);
112 if (big_valid)
113 pte_addr[gmmu_page_size_big] =
114 gk20a_mm_iova_addr(big_pte->sgt->sgl);
115
116 pde_v[0] = gmmu_pde_size_full_f();
117 pde_v[0] |= gmmu_pde_aperture_big_invalid_f();
118 pde_v[1] |= gmmu_pde_aperture_small_invalid_f() |
119 gmmu_pde_vol_big_true_f();
120
121 pde = pde_from_index(vm, i);
122
123 gk20a_mem_wr32(pde, 0, pde_v[0]);
124 gk20a_mem_wr32(pde, 1, pde_v[1]);
125
126 smp_mb();
127
128 FLUSH_CPU_DCACHE(pde,
129 sg_phys(vm->pdes.sgt->sgl) + (i*gmmu_pde__size_v()),
130 sizeof(u32)*2);
131
132 gk20a_mm_l2_invalidate(vm->mm->g);
133
134 gk20a_dbg(gpu_dbg_pte, "pde:%d = 0x%x,0x%08x\n", i, pde_v[1], pde_v[0]);
135
136 vm->tlb_dirty = true;
137}
138
139static bool gm20b_vm_is_pde_in_range(struct vm_gk20a *vm, u64 vaddr_lo, 93static bool gm20b_vm_is_pde_in_range(struct vm_gk20a *vm, u64 vaddr_lo,
140 u64 vaddr_hi, u32 pde) 94 u64 vaddr_hi, u32 pde)
141{ 95{
@@ -289,10 +243,6 @@ void gm20b_vm_clear_sparse(struct vm_gk20a *vm, u64 vaddr,
289 vm->mm->pde_stride_shift); 243 vm->mm->pde_stride_shift);
290 244
291 for (pde_i = pde_lo; pde_i <= pde_hi; pde_i++) { 245 for (pde_i = pde_lo; pde_i <= pde_hi; pde_i++) {
292 u32 pte_lo, pte_hi;
293 u32 pte_cur;
294 void *pte_kv_cur;
295
296 struct page_table_gk20a *pte = vm->pdes.ptes[pgsz_idx] + pde_i; 246 struct page_table_gk20a *pte = vm->pdes.ptes[pgsz_idx] + pde_i;
297 pte->ref_cnt--; 247 pte->ref_cnt--;
298 248