diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-21 15:03:11 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-30 03:05:05 -0400 |
commit | 6f6329c377ae12f0bf3790c15c582e454d90d3f9 (patch) | |
tree | dc3c461e4c90871b232c08902633eebd637dd8ea /drivers | |
parent | ec71ac29576afa676e056b42c13f073a17ba57e9 (diff) |
gpu: nvgpu: gv11b: init set_hww_esr_report_mask
gv11b has 2 SMs per TPC. Use *gpcs_tpcs_sms_hww_warp/global_esr*
registers instead of *gpcs_tpcs_sm_hww_warp/global_esr*
GPUT19X-75
Change-Id: I86c7ded32b2b69214e047e6de67a1745f2cef6f3
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1474860
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 53 |
1 files changed, 40 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 8cc1cfde..1291759f 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1106,23 +1106,18 @@ static void gr_gv11b_set_tex_in_dbg(struct gk20a *g, u32 data) | |||
1106 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); | 1106 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); |
1107 | } | 1107 | } |
1108 | 1108 | ||
1109 | |||
1110 | static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) | 1109 | static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) |
1111 | { | 1110 | { |
1112 | u32 val; | ||
1113 | |||
1114 | gk20a_dbg_fn(""); | 1111 | gk20a_dbg_fn(""); |
1115 | 1112 | ||
1116 | if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) | 1113 | if (data == NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE) { |
1117 | val = 0; | 1114 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), |
1118 | else | 1115 | 0); |
1119 | val = 0xffffffff; | 1116 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), |
1120 | 1117 | 0); | |
1121 | /* setup sm warp esr report masks */ | 1118 | } else { |
1122 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), val); | 1119 | g->ops.gr.set_hww_esr_report_mask(g); |
1123 | 1120 | } | |
1124 | /* setup sm global esr report mask */ | ||
1125 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), val); | ||
1126 | } | 1121 | } |
1127 | 1122 | ||
1128 | static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | 1123 | static int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, |
@@ -2712,6 +2707,37 @@ static int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | |||
2712 | 2707 | ||
2713 | return 0; | 2708 | return 0; |
2714 | } | 2709 | } |
2710 | |||
2711 | static void gv11b_gr_set_hww_esr_report_mask(struct gk20a *g) | ||
2712 | { | ||
2713 | |||
2714 | /* clear hww */ | ||
2715 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_r(), 0xffffffff); | ||
2716 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_r(), 0xffffffff); | ||
2717 | |||
2718 | /* setup sm warp esr report masks */ | ||
2719 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r(), | ||
2720 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_error_report_f() | | ||
2721 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_api_stack_error_report_f() | | ||
2722 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_wrap_report_f() | | ||
2723 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f() | | ||
2724 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_pc_overflow_report_f() | | ||
2725 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f() | | ||
2726 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f() | | ||
2727 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f() | | ||
2728 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_reg_report_f() | | ||
2729 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_oor_addr_report_f() | | ||
2730 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f() | | ||
2731 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f() | | ||
2732 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f() | | ||
2733 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_stack_overflow_report_f() | | ||
2734 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_mmu_fault_report_f()); | ||
2735 | |||
2736 | /* setup sm global esr report mask. vat_alarm_report is not enabled */ | ||
2737 | gk20a_writel(g, gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r(), | ||
2738 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f()); | ||
2739 | } | ||
2740 | |||
2715 | void gv11b_init_gr(struct gpu_ops *gops) | 2741 | void gv11b_init_gr(struct gpu_ops *gops) |
2716 | { | 2742 | { |
2717 | gp10b_init_gr(gops); | 2743 | gp10b_init_gr(gops); |
@@ -2779,4 +2805,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
2779 | gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; | 2805 | gops->gr.update_sm_error_state = gv11b_gr_update_sm_error_state; |
2780 | gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; | 2806 | gops->gr.set_sm_debug_mode = gv11b_gr_set_sm_debug_mode; |
2781 | gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; | 2807 | gops->gr.record_sm_error_state = gv11b_gr_record_sm_error_state; |
2808 | gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask; | ||
2782 | } | 2809 | } |