gpu: nvgpu: Remove check to disallow gv100 link0/1

On GV100, we could not enable reflck repeater at source of PLL
which is shared by link 0/1. So we do not allow link 0 and 1 to
be used on GV100. This refclk repeater is present only on GV100.
Remove the check as we currently use link3 on GV100 and do not
plan to use any other link.

JIRA NVLINK-162

Change-Id: I9ffcc0b20d084a208271d2c594ec64b5bafaabfb
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1734538
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
index e5e16e13..7258b9e9 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
@@ -791,12 +791,6 @@ static u32 gv100_nvlink_minion_init_uphy(struct gk20a *g, unsigned long mask,
 
         link_enable = __gv100_nvlink_get_link_reset_mask(g);
 
-        /* Cannot use links 0/1 without refclk buffer */
-        if (mask & (BIT(1)|BIT(0))) {
-                nvgpu_err(g, "links 0/1 not supported on GV100");
-                return -EINVAL;
-        }
-
         for_each_set_bit(link_id, &mask, 32) {
                 master_pll = g->nvlink.links[link_id].pll_master_link_id;
                 slave_pll = g->nvlink.links[link_id].pll_slave_link_id;