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author | Shardar Shariff Md <smohammed@nvidia.com> | 2016-11-01 09:43:34 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-11-11 05:18:45 -0500 |
commit | 68ff0c8f309e79266682f96994cf83c921061f77 (patch) | |
tree | b5957e737c9cf2efe8a697465e64454c65420702 /drivers | |
parent | a42d3072fba8085d6d86f9c5ce5352d0684745e7 (diff) |
gpu: nvgpu: gv11b: use fuse control read/write APIs for K4.4
Use fuse control read/write APIs when accessing fuse control registers
for Kernel version 4.4
Bug 200243956
Change-Id: I3d78ec2733b5f56615fa0b588664570c85557e63
Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
Reviewed-on: http://git-master/r/1245826
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index e6050359..ca5e8dc0 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ | 16 | #include "gk20a/gk20a.h" /* FERMI and MAXWELL classes defined here */ |
17 | #include <linux/delay.h> | 17 | #include <linux/delay.h> |
18 | #include <linux/tegra-fuse.h> | 18 | #include <linux/tegra-fuse.h> |
19 | #include <linux/version.h> | ||
19 | 20 | ||
20 | #include "gk20a/gr_gk20a.h" | 21 | #include "gk20a/gr_gk20a.h" |
21 | #include "gk20a/semaphore_gk20a.h" | 22 | #include "gk20a/semaphore_gk20a.h" |
@@ -1135,8 +1136,13 @@ static void gr_gv11b_init_cyclestats(struct gk20a *g) | |||
1135 | 1136 | ||
1136 | static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1137 | static void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1137 | { | 1138 | { |
1139 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | ||
1138 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); | 1140 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); |
1139 | tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); | 1141 | tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); |
1142 | #else | ||
1143 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); | ||
1144 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); | ||
1145 | #endif | ||
1140 | 1146 | ||
1141 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1147 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) |
1142 | tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); | 1148 | tegra_fuse_writel(0x2, FUSE_OPT_GPU_TPC0_DISABLE_0); |