gpu: nvgpu: Add GPU reset for gp106 XVE

Resets the GPU without resetting the XVE/XP interfaces. This allows
the GPU to stay attached to the PCI bus but still resets all the rest
of the GPU's internal state.

Bug 1816516

Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1287644
Reviewed-on: http://git-master/r/1287650
(cherry picked from commit c14efaee5d03a053d5bf229425a7594e1c6bfad0)
Change-Id: If7aba3cc8109e30bd6b6aa145836e812d50b35c5
Reviewed-on: http://git-master/r/1292699
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 84 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.c b/drivers/gpu/nvgpu/gp106/xve_gp106.c
index a0ee8108..561140c6 100644
--- a/drivers/gpu/nvgpu/gp106/xve_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/xve_gp106.c
@@ -59,6 +59,40 @@ static u32 xve_xve_readl_gp106(struct gk20a *g, u32 reg)
 }
 
 /**
+ * Resets the GPU (except the XVE/XP).
+ */
+static void xve_reset_gpu_gp106(struct gk20a *g)
+{
+        u32 reset;
+
+        /*
+         * This resets the GPU except for the XVE/XP (since then we would lose
+         * the dGPU from the bus). t18x has a HW limitation where once that
+         * happens the GPU is gone until the entire system is reset.
+         *
+         * We have to use the auto-deassert register since we won't be able to
+         * access the GPU after the GPU goes into reset. This appears like the
+         * GPU has dropped from the bus and causes nvgpu to reset the entire
+         * system. Whoops!
+         */
+        reset = xve_reset_reset_m() |
+                xve_reset_gpu_on_sw_reset_m() |
+                xve_reset_counter_en_m() |
+                xve_reset_counter_val_f(0x7ff) |
+                xve_reset_clock_on_sw_reset_m() |
+                xve_reset_clock_counter_en_m() |
+                xve_reset_clock_counter_val_f(0x7ff);
+
+        g->ops.xve.xve_writel(g, xve_reset_r(), reset | xve_reset_reset_m());
+
+        /*
+         * Don't access GPU until _after_ it's back out of reset!
+         */
+        msleep(100);
+        g->ops.xve.xve_writel(g, xve_reset_r(), 0);
+}
+
+/**
  * Places one of:
  *
  *   %GPU_XVE_SPEED_2P5
@@ -632,6 +666,7 @@ int gp106_init_xve_ops(struct gpu_ops *gops)
         gops->xve.xve_readl        = xve_xve_readl_gp106;
         gops->xve.xve_writel       = xve_xve_writel_gp106;
         gops->xve.disable_aspm     = xve_disable_aspm_gp106;
+        gops->xve.reset_gpu        = xve_reset_gpu_gp106;
 
         return 0;
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h
index 24434ae0..bfcb4883 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp106/hw_xve_gp106.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -146,4 +146,52 @@ static inline u32 xve_priv_xv_cya_l1_enable_v(u32 r)
 {
         return (r >> 8) & 0x1;
 }
+static inline u32 xve_reset_r(void)
+{
+        return 0x00000718;
+}
+static inline u32 xve_reset_reset_m(void)
+{
+        return 0x1 << 0;
+}
+static inline u32 xve_reset_gpu_on_sw_reset_m(void)
+{
+        return 0x1 << 1;
+}
+static inline u32 xve_reset_counter_en_m(void)
+{
+        return 0x1 << 2;
+}
+static inline u32 xve_reset_counter_val_f(u32 v)
+{
+        return (v & 0x7ff) << 4;
+}
+static inline u32 xve_reset_counter_val_m(void)
+{
+        return 0x7ff << 4;
+}
+static inline u32 xve_reset_counter_val_v(u32 r)
+{
+        return (r >> 4) & 0x7ff;
+}
+static inline u32 xve_reset_clock_on_sw_reset_m(void)
+{
+        return 0x1 << 15;
+}
+static inline u32 xve_reset_clock_counter_en_m(void)
+{
+        return 0x1 << 16;
+}
+static inline u32 xve_reset_clock_counter_val_f(u32 v)
+{
+        return (v & 0x7ff) << 17;
+}
+static inline u32 xve_reset_clock_counter_val_m(void)
+{
+        return 0x7ff << 17;
+}
+static inline u32 xve_reset_clock_counter_val_v(u32 r)
+{
+        return (r >> 17) & 0x7ff;
+}
 #endif