diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-26 13:47:16 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-27 19:34:43 -0400 |
commit | 6431ec360bf7b7baf6dd687b1525c40114ede189 (patch) | |
tree | f899b3e215bf87cc411cefaf54c9b6011e487eb4 /drivers | |
parent | 9907b97985c47003a179c4357274b737cc0699ee (diff) |
gpu: nvgpu: Reorg gr_ctx HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
gr_ctx sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I783d8e8919d8694ad2aa0d285e4c5a2b62580f48
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1527417
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 2 |
12 files changed, 39 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8135f05e..90c35a7b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -663,7 +663,6 @@ struct gpu_ops { | |||
663 | struct { | 663 | struct { |
664 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); | 664 | int (*get_netlist_name)(struct gk20a *g, int index, char *name); |
665 | bool (*is_fw_defined)(void); | 665 | bool (*is_fw_defined)(void); |
666 | bool use_dma_for_fw_bootstrap; | ||
667 | } gr_ctx; | 666 | } gr_ctx; |
668 | struct { | 667 | struct { |
669 | int (*init)(struct gk20a *g); | 668 | int (*init)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index d7c80b91..037f0df4 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2367,7 +2367,7 @@ int gr_gk20a_load_ctxsw_ucode(struct gk20a *g) | |||
2367 | * In case bootloader is not supported, revert to the old way of | 2367 | * In case bootloader is not supported, revert to the old way of |
2368 | * loading gr ucode, without the faster bootstrap routine. | 2368 | * loading gr ucode, without the faster bootstrap routine. |
2369 | */ | 2369 | */ |
2370 | if (!g->ops.gr_ctx.use_dma_for_fw_bootstrap) { | 2370 | if (!nvgpu_is_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP)) { |
2371 | gr_gk20a_load_falcon_dmem(g); | 2371 | gr_gk20a_load_falcon_dmem(g); |
2372 | gr_gk20a_load_falcon_imem(g); | 2372 | gr_gk20a_load_falcon_imem(g); |
2373 | gr_gk20a_start_falcon_ucode(g); | 2373 | gr_gk20a_start_falcon_ucode(g); |
@@ -2400,7 +2400,7 @@ static int gr_gk20a_wait_ctxsw_ready(struct gk20a *g) | |||
2400 | return ret; | 2400 | return ret; |
2401 | } | 2401 | } |
2402 | 2402 | ||
2403 | if (g->ops.gr_ctx.use_dma_for_fw_bootstrap || | 2403 | if (nvgpu_is_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP) || |
2404 | nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) | 2404 | nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) |
2405 | gk20a_writel(g, gr_fecs_current_ctx_r(), | 2405 | gk20a_writel(g, gr_fecs_current_ctx_r(), |
2406 | gr_fecs_current_ctx_valid_false_f()); | 2406 | gr_fecs_current_ctx_valid_false_f()); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.c index e22acbe3..555c1409 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GM20B Graphics Context | 4 | * GM20B Graphics Context |
5 | * | 5 | * |
6 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms and conditions of the GNU General Public License, | 9 | * under the terms and conditions of the GNU General Public License, |
@@ -22,7 +22,7 @@ | |||
22 | #include "gk20a/gk20a.h" | 22 | #include "gk20a/gk20a.h" |
23 | #include "gr_ctx_gm20b.h" | 23 | #include "gr_ctx_gm20b.h" |
24 | 24 | ||
25 | static int gr_gm20b_get_netlist_name(struct gk20a *g, int index, char *name) | 25 | int gr_gm20b_get_netlist_name(struct gk20a *g, int index, char *name) |
26 | { | 26 | { |
27 | switch (index) { | 27 | switch (index) { |
28 | #ifdef GM20B_NETLIST_IMAGE_FW_NAME | 28 | #ifdef GM20B_NETLIST_IMAGE_FW_NAME |
@@ -57,7 +57,7 @@ static int gr_gm20b_get_netlist_name(struct gk20a *g, int index, char *name) | |||
57 | return -1; | 57 | return -1; |
58 | } | 58 | } |
59 | 59 | ||
60 | static bool gr_gm20b_is_firmware_defined(void) | 60 | bool gr_gm20b_is_firmware_defined(void) |
61 | { | 61 | { |
62 | #ifdef GM20B_NETLIST_IMAGE_FW_NAME | 62 | #ifdef GM20B_NETLIST_IMAGE_FW_NAME |
63 | return true; | 63 | return true; |
@@ -65,9 +65,3 @@ static bool gr_gm20b_is_firmware_defined(void) | |||
65 | return false; | 65 | return false; |
66 | #endif | 66 | #endif |
67 | } | 67 | } |
68 | |||
69 | void gm20b_init_gr_ctx(struct gpu_ops *gops) { | ||
70 | gops->gr_ctx.get_netlist_name = gr_gm20b_get_netlist_name; | ||
71 | gops->gr_ctx.is_fw_defined = gr_gm20b_is_firmware_defined; | ||
72 | gops->gr_ctx.use_dma_for_fw_bootstrap = true; | ||
73 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h index 9172e151..414634da 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_ctx_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Graphics Context | 2 | * GM20B Graphics Context |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -24,6 +24,7 @@ | |||
24 | /*#undef GM20B_NETLIST_IMAGE_FW_NAME*/ | 24 | /*#undef GM20B_NETLIST_IMAGE_FW_NAME*/ |
25 | #define GM20B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B | 25 | #define GM20B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_B |
26 | 26 | ||
27 | void gm20b_init_gr_ctx(struct gpu_ops *gops); | 27 | int gr_gm20b_get_netlist_name(struct gk20a *g, int index, char *name); |
28 | bool gr_gm20b_is_firmware_defined(void); | ||
28 | 29 | ||
29 | #endif /*__GR_CTX_GM20B_H__*/ | 30 | #endif /*__GR_CTX_GM20B_H__*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index c89f3746..1a11b11c 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -268,6 +268,10 @@ static const struct gpu_ops gm20b_ops = { | |||
268 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | 268 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, |
269 | #endif | 269 | #endif |
270 | }, | 270 | }, |
271 | .gr_ctx = { | ||
272 | .get_netlist_name = gr_gm20b_get_netlist_name, | ||
273 | .is_fw_defined = gr_gm20b_is_firmware_defined, | ||
274 | }, | ||
271 | .mc = { | 275 | .mc = { |
272 | .intr_enable = mc_gk20a_intr_enable, | 276 | .intr_enable = mc_gk20a_intr_enable, |
273 | .intr_unit_config = mc_gk20a_intr_unit_config, | 277 | .intr_unit_config = mc_gk20a_intr_unit_config, |
@@ -339,6 +343,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
339 | gops->ce2 = gm20b_ops.ce2; | 343 | gops->ce2 = gm20b_ops.ce2; |
340 | gops->clock_gating = gm20b_ops.clock_gating; | 344 | gops->clock_gating = gm20b_ops.clock_gating; |
341 | gops->fifo = gm20b_ops.fifo; | 345 | gops->fifo = gm20b_ops.fifo; |
346 | gops->gr_ctx = gm20b_ops.gr_ctx; | ||
342 | gops->mc = gm20b_ops.mc; | 347 | gops->mc = gm20b_ops.mc; |
343 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; | 348 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; |
344 | gops->debug = gm20b_ops.debug; | 349 | gops->debug = gm20b_ops.debug; |
@@ -356,6 +361,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
356 | gm20b_ops.chip_init_gpu_characteristics; | 361 | gm20b_ops.chip_init_gpu_characteristics; |
357 | gops->get_litter_value = gm20b_ops.get_litter_value; | 362 | gops->get_litter_value = gm20b_ops.get_litter_value; |
358 | 363 | ||
364 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
359 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 365 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); |
360 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 366 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
361 | 367 | ||
@@ -389,7 +395,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
389 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 395 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
390 | gm20b_init_gr(g); | 396 | gm20b_init_gr(g); |
391 | gm20b_init_fb(gops); | 397 | gm20b_init_fb(gops); |
392 | gm20b_init_gr_ctx(gops); | ||
393 | gm20b_init_mm(gops); | 398 | gm20b_init_mm(gops); |
394 | gm20b_init_pmu_ops(g); | 399 | gm20b_init_pmu_ops(g); |
395 | gm20b_init_clk_ops(gops); | 400 | gm20b_init_clk_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c index 3a49cc60..706ff7e0 100644 --- a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c +++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP106 Graphics Context | 2 | * GP106 Graphics Context |
3 | * | 3 | * |
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -16,7 +16,7 @@ | |||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gr_ctx_gp106.h" | 17 | #include "gr_ctx_gp106.h" |
18 | 18 | ||
19 | static int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name) | 19 | int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name) |
20 | { | 20 | { |
21 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; | 21 | u32 ver = g->gpu_characteristics.arch + g->gpu_characteristics.impl; |
22 | 22 | ||
@@ -36,14 +36,7 @@ static int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name) | |||
36 | return 0; | 36 | return 0; |
37 | } | 37 | } |
38 | 38 | ||
39 | static bool gr_gp106_is_firmware_defined(void) | 39 | bool gr_gp106_is_firmware_defined(void) |
40 | { | 40 | { |
41 | return true; | 41 | return true; |
42 | } | 42 | } |
43 | |||
44 | void gp106_init_gr_ctx(struct gpu_ops *gops) | ||
45 | { | ||
46 | gops->gr_ctx.get_netlist_name = gr_gp106_get_netlist_name; | ||
47 | gops->gr_ctx.is_fw_defined = gr_gp106_is_firmware_defined; | ||
48 | gops->gr_ctx.use_dma_for_fw_bootstrap = false; | ||
49 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h index fef80abb..f1162f5e 100644 --- a/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h +++ b/drivers/gpu/nvgpu/gp106/gr_ctx_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -22,6 +22,7 @@ | |||
22 | #define GP106_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_C | 22 | #define GP106_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_C |
23 | #define GP104_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D | 23 | #define GP104_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_D |
24 | 24 | ||
25 | void gp106_init_gr_ctx(struct gpu_ops *gops); | 25 | int gr_gp106_get_netlist_name(struct gk20a *g, int index, char *name); |
26 | bool gr_gp106_is_firmware_defined(void); | ||
26 | 27 | ||
27 | #endif /*__GR_CTX_GP106_H__*/ | 28 | #endif /*__GR_CTX_GP106_H__*/ |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 227b22e6..763dab44 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -313,6 +313,10 @@ static const struct gpu_ops gp106_ops = { | |||
313 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, | 313 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, |
314 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | 314 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, |
315 | }, | 315 | }, |
316 | .gr_ctx = { | ||
317 | .get_netlist_name = gr_gp106_get_netlist_name, | ||
318 | .is_fw_defined = gr_gp106_is_firmware_defined, | ||
319 | }, | ||
316 | .mc = { | 320 | .mc = { |
317 | .intr_enable = mc_gp10b_intr_enable, | 321 | .intr_enable = mc_gp10b_intr_enable, |
318 | .intr_unit_config = mc_gp10b_intr_unit_config, | 322 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -403,6 +407,7 @@ int gp106_init_hal(struct gk20a *g) | |||
403 | gops->ce2 = gp106_ops.ce2; | 407 | gops->ce2 = gp106_ops.ce2; |
404 | gops->clock_gating = gp106_ops.clock_gating; | 408 | gops->clock_gating = gp106_ops.clock_gating; |
405 | gops->fifo = gp106_ops.fifo; | 409 | gops->fifo = gp106_ops.fifo; |
410 | gops->gr_ctx = gp106_ops.gr_ctx; | ||
406 | gops->mc = gp106_ops.mc; | 411 | gops->mc = gp106_ops.mc; |
407 | gops->debug = gp106_ops.debug; | 412 | gops->debug = gp106_ops.debug; |
408 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; | 413 | gops->dbg_session_ops = gp106_ops.dbg_session_ops; |
@@ -421,6 +426,7 @@ int gp106_init_hal(struct gk20a *g) | |||
421 | gp106_ops.chip_init_gpu_characteristics; | 426 | gp106_ops.chip_init_gpu_characteristics; |
422 | gops->bios_init = gp106_ops.bios_init; | 427 | gops->bios_init = gp106_ops.bios_init; |
423 | 428 | ||
429 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
424 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 430 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
425 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | 431 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); |
426 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 432 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
@@ -429,7 +435,6 @@ int gp106_init_hal(struct gk20a *g) | |||
429 | gp106_init_gr(g); | 435 | gp106_init_gr(g); |
430 | gp10b_init_fecs_trace_ops(gops); | 436 | gp10b_init_fecs_trace_ops(gops); |
431 | gp106_init_fb(gops); | 437 | gp106_init_fb(gops); |
432 | gp106_init_gr_ctx(gops); | ||
433 | gp106_init_mm(gops); | 438 | gp106_init_mm(gops); |
434 | gp106_init_pmu_ops(g); | 439 | gp106_init_pmu_ops(g); |
435 | gp106_init_clk_ops(gops); | 440 | gp106_init_clk_ops(gops); |
@@ -439,7 +444,6 @@ int gp106_init_hal(struct gk20a *g) | |||
439 | gp106_init_therm_ops(gops); | 444 | gp106_init_therm_ops(gops); |
440 | 445 | ||
441 | g->name = "gp10x"; | 446 | g->name = "gp10x"; |
442 | gops->gr_ctx.use_dma_for_fw_bootstrap = true; | ||
443 | 447 | ||
444 | c->twod_class = FERMI_TWOD_A; | 448 | c->twod_class = FERMI_TWOD_A; |
445 | c->threed_class = PASCAL_B; | 449 | c->threed_class = PASCAL_B; |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c index 2bb4a313..0c1798c0 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.c | |||
@@ -3,7 +3,7 @@ | |||
3 | * | 3 | * |
4 | * GM20B Graphics Context | 4 | * GM20B Graphics Context |
5 | * | 5 | * |
6 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 6 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. |
7 | * | 7 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms and conditions of the GNU General Public License, | 9 | * under the terms and conditions of the GNU General Public License, |
@@ -22,7 +22,7 @@ | |||
22 | #include "gk20a/gk20a.h" | 22 | #include "gk20a/gk20a.h" |
23 | #include "gr_ctx_gp10b.h" | 23 | #include "gr_ctx_gp10b.h" |
24 | 24 | ||
25 | static int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name) | 25 | int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name) |
26 | { | 26 | { |
27 | switch (index) { | 27 | switch (index) { |
28 | #ifdef GP10B_NETLIST_IMAGE_FW_NAME | 28 | #ifdef GP10B_NETLIST_IMAGE_FW_NAME |
@@ -57,7 +57,7 @@ static int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name) | |||
57 | return -1; | 57 | return -1; |
58 | } | 58 | } |
59 | 59 | ||
60 | static bool gr_gp10b_is_firmware_defined(void) | 60 | bool gr_gp10b_is_firmware_defined(void) |
61 | { | 61 | { |
62 | #ifdef GP10B_NETLIST_IMAGE_FW_NAME | 62 | #ifdef GP10B_NETLIST_IMAGE_FW_NAME |
63 | return true; | 63 | return true; |
@@ -65,9 +65,3 @@ static bool gr_gp10b_is_firmware_defined(void) | |||
65 | return false; | 65 | return false; |
66 | #endif | 66 | #endif |
67 | } | 67 | } |
68 | |||
69 | void gp10b_init_gr_ctx(struct gpu_ops *gops) { | ||
70 | gops->gr_ctx.get_netlist_name = gr_gp10b_get_netlist_name; | ||
71 | gops->gr_ctx.is_fw_defined = gr_gp10b_is_firmware_defined; | ||
72 | gops->gr_ctx.use_dma_for_fw_bootstrap = true; | ||
73 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h index b5c76d24..45415a01 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_ctx_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Graphics Context | 2 | * GP10B Graphics Context |
3 | * | 3 | * |
4 | * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -23,6 +23,7 @@ | |||
23 | /* production netlist, one and only one from below */ | 23 | /* production netlist, one and only one from below */ |
24 | #define GP10B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A | 24 | #define GP10B_NETLIST_IMAGE_FW_NAME GK20A_NETLIST_IMAGE_A |
25 | 25 | ||
26 | void gp10b_init_gr_ctx(struct gpu_ops *gops); | 26 | int gr_gp10b_get_netlist_name(struct gk20a *g, int index, char *name); |
27 | bool gr_gp10b_is_firmware_defined(void); | ||
27 | 28 | ||
28 | #endif /*__GR_CTX_GP10B_H__*/ | 29 | #endif /*__GR_CTX_GP10B_H__*/ |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index feac284b..80018910 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -279,6 +279,10 @@ static const struct gpu_ops gp10b_ops = { | |||
279 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, | 279 | .resetup_ramfc = gp10b_fifo_resetup_ramfc, |
280 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, | 280 | .device_info_fault_id = top_device_info_data_fault_id_enum_v, |
281 | }, | 281 | }, |
282 | .gr_ctx = { | ||
283 | .get_netlist_name = gr_gp10b_get_netlist_name, | ||
284 | .is_fw_defined = gr_gp10b_is_firmware_defined, | ||
285 | }, | ||
282 | .mc = { | 286 | .mc = { |
283 | .intr_enable = mc_gp10b_intr_enable, | 287 | .intr_enable = mc_gp10b_intr_enable, |
284 | .intr_unit_config = mc_gp10b_intr_unit_config, | 288 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -352,6 +356,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
352 | gops->ce2 = gp10b_ops.ce2; | 356 | gops->ce2 = gp10b_ops.ce2; |
353 | gops->clock_gating = gp10b_ops.clock_gating; | 357 | gops->clock_gating = gp10b_ops.clock_gating; |
354 | gops->fifo = gp10b_ops.fifo; | 358 | gops->fifo = gp10b_ops.fifo; |
359 | gops->gr_ctx = gp10b_ops.gr_ctx; | ||
355 | gops->mc = gp10b_ops.mc; | 360 | gops->mc = gp10b_ops.mc; |
356 | gops->debug = gp10b_ops.debug; | 361 | gops->debug = gp10b_ops.debug; |
357 | gops->dbg_session_ops = gp10b_ops.dbg_session_ops; | 362 | gops->dbg_session_ops = gp10b_ops.dbg_session_ops; |
@@ -369,6 +374,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
369 | gp10b_ops.chip_init_gpu_characteristics; | 374 | gp10b_ops.chip_init_gpu_characteristics; |
370 | gops->get_litter_value = gp10b_ops.get_litter_value; | 375 | gops->get_litter_value = gp10b_ops.get_litter_value; |
371 | 376 | ||
377 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | ||
372 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 378 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
373 | 379 | ||
374 | #ifdef CONFIG_TEGRA_ACR | 380 | #ifdef CONFIG_TEGRA_ACR |
@@ -412,7 +418,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
412 | gp10b_init_gr(g); | 418 | gp10b_init_gr(g); |
413 | gp10b_init_fecs_trace_ops(gops); | 419 | gp10b_init_fecs_trace_ops(gops); |
414 | gp10b_init_fb(gops); | 420 | gp10b_init_fb(gops); |
415 | gp10b_init_gr_ctx(gops); | ||
416 | gp10b_init_mm(gops); | 421 | gp10b_init_mm(gops); |
417 | gp10b_init_pmu_ops(g); | 422 | gp10b_init_pmu_ops(g); |
418 | gp10b_init_regops(gops); | 423 | gp10b_init_regops(gops); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 7aac4be9..fd29a9eb 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -27,7 +27,7 @@ struct gk20a; | |||
27 | */ | 27 | */ |
28 | #define NVGPU_IS_FMODEL 1 | 28 | #define NVGPU_IS_FMODEL 1 |
29 | #define NVGPU_DRIVER_IS_DYING 2 | 29 | #define NVGPU_DRIVER_IS_DYING 2 |
30 | 30 | #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 | |
31 | /* | 31 | /* |
32 | * MM flags. | 32 | * MM flags. |
33 | */ | 33 | */ |