diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-31 17:43:11 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-11 17:16:46 -0400 |
commit | 63b74d4b768e0c96367d4983fdd8f1db1d317d01 (patch) | |
tree | 3966af83cf9abdf687667afe120cc6648a9ed360 /drivers | |
parent | 83e49b39181a86d32f6350c65659b5892f8f7670 (diff) |
gpu: nvgpu: Reorg fb HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
fb sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: Ib746798b849810401c12abf5e9cce42d827c6fb1
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533350
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fb_gm20b.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fb_gm20b.h | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fb_gp106.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fb_gp106.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 23 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fb_gp10b.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fb_gp10b.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 22 |
9 files changed, 97 insertions, 60 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c index 47b4313b..31947ad0 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c | |||
@@ -25,7 +25,7 @@ | |||
25 | 25 | ||
26 | #define VPR_INFO_FETCH_WAIT (5) | 26 | #define VPR_INFO_FETCH_WAIT (5) |
27 | 27 | ||
28 | static void fb_gm20b_init_fs_state(struct gk20a *g) | 28 | void fb_gm20b_init_fs_state(struct gk20a *g) |
29 | { | 29 | { |
30 | gk20a_dbg_info("initialize gm20b fb"); | 30 | gk20a_dbg_info("initialize gm20b fb"); |
31 | 31 | ||
@@ -434,7 +434,7 @@ void gm20b_init_kind_attr(void) | |||
434 | } | 434 | } |
435 | } | 435 | } |
436 | 436 | ||
437 | static void gm20b_fb_set_mmu_page_size(struct gk20a *g) | 437 | void gm20b_fb_set_mmu_page_size(struct gk20a *g) |
438 | { | 438 | { |
439 | /* set large page size in fb */ | 439 | /* set large page size in fb */ |
440 | u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r()); | 440 | u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r()); |
@@ -442,7 +442,7 @@ static void gm20b_fb_set_mmu_page_size(struct gk20a *g) | |||
442 | gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl); | 442 | gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl); |
443 | } | 443 | } |
444 | 444 | ||
445 | static bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g) | 445 | bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g) |
446 | { | 446 | { |
447 | /* set large page size in fb */ | 447 | /* set large page size in fb */ |
448 | u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r()); | 448 | u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r()); |
@@ -452,17 +452,17 @@ static bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g) | |||
452 | return true; | 452 | return true; |
453 | } | 453 | } |
454 | 454 | ||
455 | static unsigned int gm20b_fb_compression_page_size(struct gk20a *g) | 455 | unsigned int gm20b_fb_compression_page_size(struct gk20a *g) |
456 | { | 456 | { |
457 | return SZ_128K; | 457 | return SZ_128K; |
458 | } | 458 | } |
459 | 459 | ||
460 | static unsigned int gm20b_fb_compressible_page_size(struct gk20a *g) | 460 | unsigned int gm20b_fb_compressible_page_size(struct gk20a *g) |
461 | { | 461 | { |
462 | return SZ_64K; | 462 | return SZ_64K; |
463 | } | 463 | } |
464 | 464 | ||
465 | static void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) | 465 | void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) |
466 | { | 466 | { |
467 | u32 val; | 467 | u32 val; |
468 | 468 | ||
@@ -511,7 +511,7 @@ static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g, | |||
511 | return -ETIMEDOUT; | 511 | return -ETIMEDOUT; |
512 | } | 512 | } |
513 | 513 | ||
514 | static int gm20b_fb_vpr_info_fetch(struct gk20a *g) | 514 | int gm20b_fb_vpr_info_fetch(struct gk20a *g) |
515 | { | 515 | { |
516 | if (gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) { | 516 | if (gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) { |
517 | return -ETIME; | 517 | return -ETIME; |
@@ -523,14 +523,14 @@ static int gm20b_fb_vpr_info_fetch(struct gk20a *g) | |||
523 | return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); | 523 | return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); |
524 | } | 524 | } |
525 | 525 | ||
526 | static bool gm20b_fb_debug_mode_enabled(struct gk20a *g) | 526 | bool gm20b_fb_debug_mode_enabled(struct gk20a *g) |
527 | { | 527 | { |
528 | u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | 528 | u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); |
529 | return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) == | 529 | return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) == |
530 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); | 530 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); |
531 | } | 531 | } |
532 | 532 | ||
533 | static void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | 533 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) |
534 | { | 534 | { |
535 | u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; | 535 | u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; |
536 | 536 | ||
@@ -554,21 +554,3 @@ static void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | |||
554 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); | 554 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); |
555 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); | 555 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); |
556 | } | 556 | } |
557 | |||
558 | void gm20b_init_fb(struct gpu_ops *gops) | ||
559 | { | ||
560 | gops->fb.reset = fb_gk20a_reset; | ||
561 | gops->fb.init_hw = gk20a_fb_init_hw; | ||
562 | gops->fb.init_fs_state = fb_gm20b_init_fs_state; | ||
563 | gops->fb.set_mmu_page_size = gm20b_fb_set_mmu_page_size; | ||
564 | gops->fb.set_use_full_comp_tag_line = gm20b_fb_set_use_full_comp_tag_line; | ||
565 | gops->fb.compression_page_size = gm20b_fb_compression_page_size; | ||
566 | gops->fb.compressible_page_size = gm20b_fb_compressible_page_size; | ||
567 | gops->fb.vpr_info_fetch = gm20b_fb_vpr_info_fetch; | ||
568 | gops->fb.dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info; | ||
569 | gops->fb.is_debug_mode_enabled = gm20b_fb_debug_mode_enabled; | ||
570 | gops->fb.set_debug_mode = gm20b_fb_set_debug_mode; | ||
571 | gops->fb.tlb_invalidate = gk20a_fb_tlb_invalidate; | ||
572 | gm20b_init_uncompressed_kind_map(); | ||
573 | gm20b_init_kind_attr(); | ||
574 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.h b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h index 22b848d6..42e86407 100644 --- a/drivers/gpu/nvgpu/gm20b/fb_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B FB | 2 | * GM20B FB |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -17,7 +17,16 @@ | |||
17 | #define _NVHOST_GM20B_FB | 17 | #define _NVHOST_GM20B_FB |
18 | struct gk20a; | 18 | struct gk20a; |
19 | 19 | ||
20 | void gm20b_init_fb(struct gpu_ops *gops); | 20 | void fb_gm20b_init_fs_state(struct gk20a *g); |
21 | void gm20b_fb_set_mmu_page_size(struct gk20a *g); | ||
22 | bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g); | ||
23 | unsigned int gm20b_fb_compression_page_size(struct gk20a *g); | ||
24 | unsigned int gm20b_fb_compressible_page_size(struct gk20a *g); | ||
25 | void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g); | ||
26 | int gm20b_fb_vpr_info_fetch(struct gk20a *g); | ||
27 | bool gm20b_fb_debug_mode_enabled(struct gk20a *g); | ||
28 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable); | ||
29 | |||
21 | void gm20b_init_uncompressed_kind_map(void); | 30 | void gm20b_init_uncompressed_kind_map(void); |
22 | void gm20b_init_kind_attr(void); | 31 | void gm20b_init_kind_attr(void); |
23 | #endif | 32 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 7861e438..a540de64 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -16,6 +16,7 @@ | |||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/ce2_gk20a.h" | 17 | #include "gk20a/ce2_gk20a.h" |
18 | #include "gk20a/dbg_gpu_gk20a.h" | 18 | #include "gk20a/dbg_gpu_gk20a.h" |
19 | #include "gk20a/fb_gk20a.h" | ||
19 | #include "gk20a/fifo_gk20a.h" | 20 | #include "gk20a/fifo_gk20a.h" |
20 | #include "gk20a/therm_gk20a.h" | 21 | #include "gk20a/therm_gk20a.h" |
21 | #include "gk20a/css_gr_gk20a.h" | 22 | #include "gk20a/css_gr_gk20a.h" |
@@ -161,6 +162,21 @@ static const struct gpu_ops gm20b_ops = { | |||
161 | .isr_stall = gk20a_ce2_isr, | 162 | .isr_stall = gk20a_ce2_isr, |
162 | .isr_nonstall = gk20a_ce2_nonstall_isr, | 163 | .isr_nonstall = gk20a_ce2_nonstall_isr, |
163 | }, | 164 | }, |
165 | .fb = { | ||
166 | .reset = fb_gk20a_reset, | ||
167 | .init_hw = gk20a_fb_init_hw, | ||
168 | .init_fs_state = fb_gm20b_init_fs_state, | ||
169 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
170 | .set_use_full_comp_tag_line = | ||
171 | gm20b_fb_set_use_full_comp_tag_line, | ||
172 | .compression_page_size = gm20b_fb_compression_page_size, | ||
173 | .compressible_page_size = gm20b_fb_compressible_page_size, | ||
174 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
175 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
176 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | ||
177 | .set_debug_mode = gm20b_fb_set_debug_mode, | ||
178 | .tlb_invalidate = gk20a_fb_tlb_invalidate, | ||
179 | }, | ||
164 | .clock_gating = { | 180 | .clock_gating = { |
165 | .slcg_bus_load_gating_prod = | 181 | .slcg_bus_load_gating_prod = |
166 | gm20b_slcg_bus_load_gating_prod, | 182 | gm20b_slcg_bus_load_gating_prod, |
@@ -378,6 +394,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
378 | 394 | ||
379 | gops->ltc = gm20b_ops.ltc; | 395 | gops->ltc = gm20b_ops.ltc; |
380 | gops->ce2 = gm20b_ops.ce2; | 396 | gops->ce2 = gm20b_ops.ce2; |
397 | gops->fb = gm20b_ops.fb; | ||
381 | gops->clock_gating = gm20b_ops.clock_gating; | 398 | gops->clock_gating = gm20b_ops.clock_gating; |
382 | gops->fifo = gm20b_ops.fifo; | 399 | gops->fifo = gm20b_ops.fifo; |
383 | gops->gr_ctx = gm20b_ops.gr_ctx; | 400 | gops->gr_ctx = gm20b_ops.gr_ctx; |
@@ -445,10 +462,12 @@ int gm20b_init_hal(struct gk20a *g) | |||
445 | #endif | 462 | #endif |
446 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 463 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
447 | gm20b_init_gr(g); | 464 | gm20b_init_gr(g); |
448 | gm20b_init_fb(gops); | ||
449 | gm20b_init_mm(gops); | 465 | gm20b_init_mm(gops); |
450 | gm20b_init_pmu_ops(g); | 466 | gm20b_init_pmu_ops(g); |
451 | 467 | ||
468 | gm20b_init_uncompressed_kind_map(); | ||
469 | gm20b_init_kind_attr(); | ||
470 | |||
452 | g->name = "gm20b"; | 471 | g->name = "gm20b"; |
453 | 472 | ||
454 | c->twod_class = FERMI_TWOD_A; | 473 | c->twod_class = FERMI_TWOD_A; |
diff --git a/drivers/gpu/nvgpu/gp106/fb_gp106.c b/drivers/gpu/nvgpu/gp106/fb_gp106.c index 5be7062d..25055e79 100644 --- a/drivers/gpu/nvgpu/gp106/fb_gp106.c +++ b/drivers/gpu/nvgpu/gp106/fb_gp106.c | |||
@@ -21,7 +21,7 @@ | |||
21 | #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ | 21 | #define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ |
22 | #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ | 22 | #define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ |
23 | 23 | ||
24 | static void gp106_fb_reset(struct gk20a *g) | 24 | void gp106_fb_reset(struct gk20a *g) |
25 | { | 25 | { |
26 | u32 val; | 26 | u32 val; |
27 | 27 | ||
@@ -40,11 +40,3 @@ static void gp106_fb_reset(struct gk20a *g) | |||
40 | val &= ~fb_mmu_priv_level_mask_write_violation_m(); | 40 | val &= ~fb_mmu_priv_level_mask_write_violation_m(); |
41 | gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); | 41 | gk20a_writel(g, fb_mmu_priv_level_mask_r(), val); |
42 | } | 42 | } |
43 | |||
44 | void gp106_init_fb(struct gpu_ops *gops) | ||
45 | { | ||
46 | gp10b_init_fb(gops); | ||
47 | |||
48 | gops->fb.init_fs_state = NULL; | ||
49 | gops->fb.reset = gp106_fb_reset; | ||
50 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/fb_gp106.h b/drivers/gpu/nvgpu/gp106/fb_gp106.h index 87b371e1..99a70d7b 100644 --- a/drivers/gpu/nvgpu/gp106/fb_gp106.h +++ b/drivers/gpu/nvgpu/gp106/fb_gp106.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -15,5 +15,5 @@ | |||
15 | #define FB_GP106_H | 15 | #define FB_GP106_H |
16 | struct gpu_ops; | 16 | struct gpu_ops; |
17 | 17 | ||
18 | void gp106_init_fb(struct gpu_ops *gops); | 18 | void gp106_fb_reset(struct gk20a *g); |
19 | #endif | 19 | #endif |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 4a891a82..361a7b0f 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "gk20a/flcn_gk20a.h" | 24 | #include "gk20a/flcn_gk20a.h" |
25 | #include "gk20a/regops_gk20a.h" | 25 | #include "gk20a/regops_gk20a.h" |
26 | #include "gk20a/mc_gk20a.h" | 26 | #include "gk20a/mc_gk20a.h" |
27 | #include "gk20a/fb_gk20a.h" | ||
27 | 28 | ||
28 | #include "gp10b/ltc_gp10b.h" | 29 | #include "gp10b/ltc_gp10b.h" |
29 | #include "gp10b/gr_gp10b.h" | 30 | #include "gp10b/gr_gp10b.h" |
@@ -35,6 +36,7 @@ | |||
35 | #include "gp10b/cde_gp10b.h" | 36 | #include "gp10b/cde_gp10b.h" |
36 | #include "gp10b/priv_ring_gp10b.h" | 37 | #include "gp10b/priv_ring_gp10b.h" |
37 | #include "gp10b/fifo_gp10b.h" | 38 | #include "gp10b/fifo_gp10b.h" |
39 | #include "gp10b/fb_gp10b.h" | ||
38 | 40 | ||
39 | #include "gp106/fifo_gp106.h" | 41 | #include "gp106/fifo_gp106.h" |
40 | #include "gp106/regops_gp106.h" | 42 | #include "gp106/regops_gp106.h" |
@@ -43,6 +45,7 @@ | |||
43 | #include "gm20b/gr_gm20b.h" | 45 | #include "gm20b/gr_gm20b.h" |
44 | #include "gm20b/fifo_gm20b.h" | 46 | #include "gm20b/fifo_gm20b.h" |
45 | #include "gm20b/pmu_gm20b.h" | 47 | #include "gm20b/pmu_gm20b.h" |
48 | #include "gm20b/fb_gm20b.h" | ||
46 | 49 | ||
47 | #include "gp106/clk_gp106.h" | 50 | #include "gp106/clk_gp106.h" |
48 | #include "gp106/clk_arb_gp106.h" | 51 | #include "gp106/clk_arb_gp106.h" |
@@ -210,6 +213,21 @@ static const struct gpu_ops gp106_ops = { | |||
210 | .isr_stall = gp10b_ce_isr, | 213 | .isr_stall = gp10b_ce_isr, |
211 | .isr_nonstall = gp10b_ce_nonstall_isr, | 214 | .isr_nonstall = gp10b_ce_nonstall_isr, |
212 | }, | 215 | }, |
216 | .fb = { | ||
217 | .reset = gp106_fb_reset, | ||
218 | .init_hw = gk20a_fb_init_hw, | ||
219 | .init_fs_state = NULL, | ||
220 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
221 | .set_use_full_comp_tag_line = | ||
222 | gm20b_fb_set_use_full_comp_tag_line, | ||
223 | .compression_page_size = gp10b_fb_compression_page_size, | ||
224 | .compressible_page_size = gp10b_fb_compressible_page_size, | ||
225 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
226 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
227 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | ||
228 | .set_debug_mode = gm20b_fb_set_debug_mode, | ||
229 | .tlb_invalidate = gk20a_fb_tlb_invalidate, | ||
230 | }, | ||
213 | .clock_gating = { | 231 | .clock_gating = { |
214 | .slcg_bus_load_gating_prod = | 232 | .slcg_bus_load_gating_prod = |
215 | gp106_slcg_bus_load_gating_prod, | 233 | gp106_slcg_bus_load_gating_prod, |
@@ -479,6 +497,7 @@ int gp106_init_hal(struct gk20a *g) | |||
479 | 497 | ||
480 | gops->ltc = gp106_ops.ltc; | 498 | gops->ltc = gp106_ops.ltc; |
481 | gops->ce2 = gp106_ops.ce2; | 499 | gops->ce2 = gp106_ops.ce2; |
500 | gops->fb = gp106_ops.fb; | ||
482 | gops->clock_gating = gp106_ops.clock_gating; | 501 | gops->clock_gating = gp106_ops.clock_gating; |
483 | gops->fifo = gp106_ops.fifo; | 502 | gops->fifo = gp106_ops.fifo; |
484 | gops->gr_ctx = gp106_ops.gr_ctx; | 503 | gops->gr_ctx = gp106_ops.gr_ctx; |
@@ -524,10 +543,12 @@ int gp106_init_hal(struct gk20a *g) | |||
524 | 543 | ||
525 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 544 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
526 | gp106_init_gr(g); | 545 | gp106_init_gr(g); |
527 | gp106_init_fb(gops); | ||
528 | gp106_init_mm(gops); | 546 | gp106_init_mm(gops); |
529 | gp106_init_pmu_ops(g); | 547 | gp106_init_pmu_ops(g); |
530 | 548 | ||
549 | gp10b_init_uncompressed_kind_map(); | ||
550 | gp10b_init_kind_attr(); | ||
551 | |||
531 | g->name = "gp10x"; | 552 | g->name = "gp10x"; |
532 | 553 | ||
533 | c->twod_class = FERMI_TWOD_A; | 554 | c->twod_class = FERMI_TWOD_A; |
diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c index 8ba9ff8e..775dc5c9 100644 --- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.c | |||
@@ -20,7 +20,7 @@ | |||
20 | 20 | ||
21 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> | 21 | #include <nvgpu/hw/gp10b/hw_gmmu_gp10b.h> |
22 | 22 | ||
23 | static noinline_for_stack void gp10b_init_uncompressed_kind_map(void) | 23 | noinline_for_stack void gp10b_init_uncompressed_kind_map(void) |
24 | { | 24 | { |
25 | int i; | 25 | int i; |
26 | 26 | ||
@@ -438,7 +438,7 @@ static noinline_for_stack bool gp10b_kind_zbc(u8 k) | |||
438 | k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); | 438 | k <= gmmu_pte_kind_c128_ms8_ms16_2cr_v()); |
439 | } | 439 | } |
440 | 440 | ||
441 | static void gp10b_init_kind_attr(void) | 441 | void gp10b_init_kind_attr(void) |
442 | { | 442 | { |
443 | u16 k; | 443 | u16 k; |
444 | 444 | ||
@@ -456,22 +456,12 @@ static void gp10b_init_kind_attr(void) | |||
456 | } | 456 | } |
457 | } | 457 | } |
458 | 458 | ||
459 | static unsigned int gp10b_fb_compression_page_size(struct gk20a *g) | 459 | unsigned int gp10b_fb_compression_page_size(struct gk20a *g) |
460 | { | 460 | { |
461 | return SZ_64K; | 461 | return SZ_64K; |
462 | } | 462 | } |
463 | 463 | ||
464 | static unsigned int gp10b_fb_compressible_page_size(struct gk20a *g) | 464 | unsigned int gp10b_fb_compressible_page_size(struct gk20a *g) |
465 | { | 465 | { |
466 | return SZ_4K; | 466 | return SZ_4K; |
467 | } | 467 | } |
468 | |||
469 | void gp10b_init_fb(struct gpu_ops *gops) | ||
470 | { | ||
471 | gm20b_init_fb(gops); | ||
472 | gops->fb.compression_page_size = gp10b_fb_compression_page_size; | ||
473 | gops->fb.compressible_page_size = gp10b_fb_compressible_page_size; | ||
474 | |||
475 | gp10b_init_uncompressed_kind_map(); | ||
476 | gp10b_init_kind_attr(); | ||
477 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h index 76efd331..626cf54d 100644 --- a/drivers/gpu/nvgpu/gp10b/fb_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/fb_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B FB | 2 | * GP10B FB |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -15,7 +15,11 @@ | |||
15 | 15 | ||
16 | #ifndef _NVGPU_GP10B_FB | 16 | #ifndef _NVGPU_GP10B_FB |
17 | #define _NVGPU_GP10B_FB | 17 | #define _NVGPU_GP10B_FB |
18 | struct gpu_ops; | 18 | struct gk20a; |
19 | |||
20 | noinline_for_stack void gp10b_init_uncompressed_kind_map(void); | ||
21 | void gp10b_init_kind_attr(void); | ||
22 | unsigned int gp10b_fb_compression_page_size(struct gk20a *g); | ||
23 | unsigned int gp10b_fb_compressible_page_size(struct gk20a *g); | ||
19 | 24 | ||
20 | void gp10b_init_fb(struct gpu_ops *gops); | ||
21 | #endif | 25 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 197c4fad..b0871155 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "gk20a/flcn_gk20a.h" | 24 | #include "gk20a/flcn_gk20a.h" |
25 | #include "gk20a/regops_gk20a.h" | 25 | #include "gk20a/regops_gk20a.h" |
26 | #include "gk20a/mc_gk20a.h" | 26 | #include "gk20a/mc_gk20a.h" |
27 | #include "gk20a/fb_gk20a.h" | ||
27 | 28 | ||
28 | #include "gp10b/gr_gp10b.h" | 29 | #include "gp10b/gr_gp10b.h" |
29 | #include "gp10b/fecs_trace_gp10b.h" | 30 | #include "gp10b/fecs_trace_gp10b.h" |
@@ -47,6 +48,7 @@ | |||
47 | #include "gm20b/pmu_gm20b.h" | 48 | #include "gm20b/pmu_gm20b.h" |
48 | #include "gm20b/clk_gm20b.h" | 49 | #include "gm20b/clk_gm20b.h" |
49 | #include "gm20b/fifo_gm20b.h" | 50 | #include "gm20b/fifo_gm20b.h" |
51 | #include "gm20b/fb_gm20b.h" | ||
50 | 52 | ||
51 | #include "gp10b.h" | 53 | #include "gp10b.h" |
52 | #include "hal_gp10b.h" | 54 | #include "hal_gp10b.h" |
@@ -170,6 +172,21 @@ static const struct gpu_ops gp10b_ops = { | |||
170 | .isr_stall = gp10b_ce_isr, | 172 | .isr_stall = gp10b_ce_isr, |
171 | .isr_nonstall = gp10b_ce_nonstall_isr, | 173 | .isr_nonstall = gp10b_ce_nonstall_isr, |
172 | }, | 174 | }, |
175 | .fb = { | ||
176 | .reset = fb_gk20a_reset, | ||
177 | .init_hw = gk20a_fb_init_hw, | ||
178 | .init_fs_state = fb_gm20b_init_fs_state, | ||
179 | .set_mmu_page_size = gm20b_fb_set_mmu_page_size, | ||
180 | .set_use_full_comp_tag_line = | ||
181 | gm20b_fb_set_use_full_comp_tag_line, | ||
182 | .compression_page_size = gp10b_fb_compression_page_size, | ||
183 | .compressible_page_size = gp10b_fb_compressible_page_size, | ||
184 | .vpr_info_fetch = gm20b_fb_vpr_info_fetch, | ||
185 | .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info, | ||
186 | .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled, | ||
187 | .set_debug_mode = gm20b_fb_set_debug_mode, | ||
188 | .tlb_invalidate = gk20a_fb_tlb_invalidate, | ||
189 | }, | ||
173 | .clock_gating = { | 190 | .clock_gating = { |
174 | .slcg_bus_load_gating_prod = | 191 | .slcg_bus_load_gating_prod = |
175 | gp10b_slcg_bus_load_gating_prod, | 192 | gp10b_slcg_bus_load_gating_prod, |
@@ -405,6 +422,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
405 | 422 | ||
406 | gops->ltc = gp10b_ops.ltc; | 423 | gops->ltc = gp10b_ops.ltc; |
407 | gops->ce2 = gp10b_ops.ce2; | 424 | gops->ce2 = gp10b_ops.ce2; |
425 | gops->fb = gp10b_ops.fb; | ||
408 | gops->clock_gating = gp10b_ops.clock_gating; | 426 | gops->clock_gating = gp10b_ops.clock_gating; |
409 | gops->fifo = gp10b_ops.fifo; | 427 | gops->fifo = gp10b_ops.fifo; |
410 | gops->gr_ctx = gp10b_ops.gr_ctx; | 428 | gops->gr_ctx = gp10b_ops.gr_ctx; |
@@ -471,10 +489,12 @@ int gp10b_init_hal(struct gk20a *g) | |||
471 | 489 | ||
472 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 490 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
473 | gp10b_init_gr(g); | 491 | gp10b_init_gr(g); |
474 | gp10b_init_fb(gops); | ||
475 | gp10b_init_mm(gops); | 492 | gp10b_init_mm(gops); |
476 | gp10b_init_pmu_ops(g); | 493 | gp10b_init_pmu_ops(g); |
477 | 494 | ||
495 | gp10b_init_uncompressed_kind_map(); | ||
496 | gp10b_init_kind_attr(); | ||
497 | |||
478 | g->name = "gp10b"; | 498 | g->name = "gp10b"; |
479 | 499 | ||
480 | c->twod_class = FERMI_TWOD_A; | 500 | c->twod_class = FERMI_TWOD_A; |