gpu: nvgpu: remove ctx header desc type

The graphics subctx header object is nothing but memory. Drop the
dependency to gr header file in the channel header file and substitute
struct nvgpu_mem for struct ctx_header_desc.

Jira NVGPU-967

Change-Id: Ic3976391016c42d2ada4aac3e0851a1222244ce9
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1807370
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

8 files changed, 41 insertions, 52 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index f7515294..2a1fd03f 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -29,8 +29,8 @@
 #include <nvgpu/timers.h>
 #include <nvgpu/cond.h>
 #include <nvgpu/atomic.h>
+#include <nvgpu/nvgpu_mem.h>
 
-#include "gr_gk20a.h"
 
 struct gk20a;
 struct dbg_session_gk20a;
@@ -266,7 +266,7 @@ struct channel_gk20a {
         u64 virt_ctx;
 #endif
 
-        struct ctx_header_desc ctx_header;
+        struct nvgpu_mem ctx_header;
 
         /* Any operating system specific data. */
         void *os_priv;
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
index b4a241e4..78b753d1 100644
--- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c
@@ -669,7 +669,7 @@ int gk20a_fecs_trace_bind_channel(struct gk20a *g,
                         GK20A_FECS_TRACE_NUM_RECORDS));
 
         if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_VA))
-                mem = &ch->ctx_header.mem;
+                mem = &ch->ctx_header;
 
         nvgpu_mem_wr(g, mem,
                 ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(),
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index dbf9ff05..ead5d34a 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -808,8 +808,7 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c)
         struct tsg_gk20a *tsg;
         struct nvgpu_gr_ctx *gr_ctx = NULL;
         struct nvgpu_mem *mem = NULL;
-        struct ctx_header_desc *ctx = &c->ctx_header;
-        struct nvgpu_mem *ctxheader = &ctx->mem;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         int ret = 0;
 
         nvgpu_log_fn(g, " ");
@@ -1683,8 +1682,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g,
         struct pm_ctx_desc *pm_ctx;
         u32 data;
         u64 virt_addr = 0;
-        struct ctx_header_desc *ctx = &c->ctx_header;
-        struct nvgpu_mem *ctxheader = &ctx->mem;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         int ret;
 
         nvgpu_log_fn(g, " ");
@@ -6620,8 +6618,7 @@ static int gr_gk20a_ctx_patch_smpc(struct gk20a *g,
         u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
         struct tsg_gk20a *tsg;
         struct nvgpu_gr_ctx *gr_ctx;
-        struct ctx_header_desc *ctx = &ch->ctx_header;
-        struct nvgpu_mem *ctxheader = &ctx->mem;
+        struct nvgpu_mem *ctxheader = &ch->ctx_header;
 
         tsg = tsg_gk20a_from_ch(ch);
         if (!tsg)
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index bd5e625d..0d32cca3 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -434,10 +434,6 @@ struct gr_gk20a {
 
 void gk20a_fecs_dump_falcon_stats(struct gk20a *g);
 
-struct ctx_header_desc {
-        struct nvgpu_mem mem;
-};
-
 /* contexts associated with a TSG */
 struct nvgpu_gr_ctx {
         struct nvgpu_mem mem;
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index f5377bc3..0aa32f8a 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1183,8 +1183,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g,
 {
         struct tsg_gk20a *tsg;
         struct nvgpu_gr_ctx *gr_ctx;
-        struct ctx_header_desc *ctx = &c->ctx_header;
-        struct nvgpu_mem *ctxheader = &ctx->mem;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         u32 gfxp_preempt_option =
                 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f();
         u32 cilp_preempt_option =
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 296d8e90..9a6afa3e 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1682,8 +1682,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g,
 {
         struct tsg_gk20a *tsg;
         struct nvgpu_gr_ctx *gr_ctx;
-        struct ctx_header_desc *ctx = &c->ctx_header;
-        struct nvgpu_mem *ctxheader = &ctx->mem;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         u32 gfxp_preempt_option =
                 ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f();
         u32 cilp_preempt_option =
@@ -2897,7 +2896,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
 {
         u32 addr_lo;
         u32 addr_hi;
-        struct ctx_header_desc *ctx;
+        struct nvgpu_mem *ctxheader;
         int err;
         struct gk20a *g = c->g;
 
@@ -2913,9 +2912,9 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va)
                 return err;
         }
 
-        ctx = &c->ctx_header;
-        addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v();
-        addr_hi = u64_hi32(ctx->mem.gpu_va);
+        ctxheader = &c->ctx_header;
+        addr_lo = u64_lo32(ctxheader->gpu_va) >> ram_in_base_shift_v();
+        addr_hi = u64_hi32(ctxheader->gpu_va);
 
         /* point this address to engine_wfi_ptr */
         nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(),
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
index d742e8dc..4e429567 100644
--- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c
@@ -43,42 +43,42 @@ static void gv11b_subctx_commit_pdb(struct vm_gk20a *vm,
 
 void gv11b_free_subctx_header(struct channel_gk20a *c)
 {
-        struct ctx_header_desc *ctx = &c->ctx_header;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         struct gk20a *g = c->g;
 
         nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header");
 
-        if (ctx->mem.gpu_va) {
-                nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va);
+        if (ctxheader->gpu_va) {
+                nvgpu_gmmu_unmap(c->vm, ctxheader, ctxheader->gpu_va);
 
-                nvgpu_dma_free(g, &ctx->mem);
+                nvgpu_dma_free(g, ctxheader);
         }
 }
 
 int gv11b_alloc_subctx_header(struct channel_gk20a *c)
 {
-        struct ctx_header_desc *ctx = &c->ctx_header;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         struct gk20a *g = c->g;
         int ret = 0;
 
         nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header");
 
-        if (!nvgpu_mem_is_valid(&ctx->mem)) {
+        if (!nvgpu_mem_is_valid(ctxheader)) {
                 ret = nvgpu_dma_alloc_sys(g, ctxsw_prog_fecs_header_v(),
-                                &ctx->mem);
+                                ctxheader);
                 if (ret) {
                         nvgpu_err(g, "failed to allocate sub ctx header");
                         return ret;
                 }
-                ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm,
-                                        &ctx->mem,
-                                        ctx->mem.size,
+                ctxheader->gpu_va = nvgpu_gmmu_map(c->vm,
+                                        ctxheader,
+                                        ctxheader->size,
                                         0, /* not GPU-cacheable */
                                         gk20a_mem_flag_none, true,
-                                        ctx->mem.aperture);
-                if (!ctx->mem.gpu_va) {
+                                        ctxheader->aperture);
+                if (!ctxheader->gpu_va) {
                         nvgpu_err(g, "failed to map ctx header");
-                        nvgpu_dma_free(g, &ctx->mem);
+                        nvgpu_dma_free(g, ctxheader);
                         return -ENOMEM;
                 }
         }
@@ -96,8 +96,7 @@ void gv11b_init_subcontext_pdb(struct vm_gk20a *vm,
 
 int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va)
 {
-        struct ctx_header_desc *ctx = &c->ctx_header;
-        struct nvgpu_mem *gr_mem;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         struct gk20a *g = c->g;
         int ret = 0;
         u32 addr_lo, addr_hi;
@@ -111,40 +110,39 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va)
 
         gr_ctx = &tsg->gr_ctx;
 
-        gr_mem = &ctx->mem;
         g->ops.mm.l2_flush(g, true);
 
         /* set priv access map */
         addr_lo = u64_lo32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]);
         addr_hi = u64_hi32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]);
-        nvgpu_mem_wr(g, gr_mem,
+        nvgpu_mem_wr(g, ctxheader,
                 ctxsw_prog_main_image_priv_access_map_addr_lo_o(),
                 addr_lo);
-        nvgpu_mem_wr(g, gr_mem,
+        nvgpu_mem_wr(g, ctxheader,
                 ctxsw_prog_main_image_priv_access_map_addr_hi_o(),
                 addr_hi);
 
         addr_lo = u64_lo32(gr_ctx->patch_ctx.mem.gpu_va);
         addr_hi = u64_hi32(gr_ctx->patch_ctx.mem.gpu_va);
-        nvgpu_mem_wr(g, gr_mem,
+        nvgpu_mem_wr(g, ctxheader,
                 ctxsw_prog_main_image_patch_adr_lo_o(),
                 addr_lo);
-        nvgpu_mem_wr(g, gr_mem,
+        nvgpu_mem_wr(g, ctxheader,
                 ctxsw_prog_main_image_patch_adr_hi_o(),
                 addr_hi);
 
-        g->ops.gr.write_pm_ptr(g, gr_mem, gr_ctx->pm_ctx.mem.gpu_va);
-        g->ops.gr.write_zcull_ptr(g, gr_mem, gr_ctx->zcull_ctx.gpu_va);
+        g->ops.gr.write_pm_ptr(g, ctxheader, gr_ctx->pm_ctx.mem.gpu_va);
+        g->ops.gr.write_zcull_ptr(g, ctxheader, gr_ctx->zcull_ctx.gpu_va);
 
         addr_lo = u64_lo32(gpu_va);
         addr_hi = u64_hi32(gpu_va);
 
-        nvgpu_mem_wr(g, gr_mem,
+        nvgpu_mem_wr(g, ctxheader,
                 ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi);
-        nvgpu_mem_wr(g, gr_mem,
+        nvgpu_mem_wr(g, ctxheader,
                 ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo);
 
-        nvgpu_mem_wr(g, gr_mem,
+        nvgpu_mem_wr(g, ctxheader,
                 ctxsw_prog_main_image_ctl_o(),
                 ctxsw_prog_main_image_ctl_type_per_veid_header_v());
 
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c
index b536d15e..b5272ae1 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c
@@ -29,7 +29,7 @@
 
 int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
 {
-        struct ctx_header_desc *ctx = &c->ctx_header;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         struct tegra_vgpu_cmd_msg msg = {};
         struct tegra_vgpu_alloc_ctx_header_params *p =
                                 &msg.params.alloc_ctx_header;
@@ -53,20 +53,20 @@ int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c)
                         GMMU_PAGE_SIZE_KERNEL);
                 return err;
         }
-        ctx->mem.gpu_va = p->ctx_header_va;
+        ctxheader->gpu_va = p->ctx_header_va;
 
         return err;
 }
 
 void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
 {
-        struct ctx_header_desc *ctx = &c->ctx_header;
+        struct nvgpu_mem *ctxheader = &c->ctx_header;
         struct tegra_vgpu_cmd_msg msg = {};
         struct tegra_vgpu_free_ctx_header_params *p =
                                 &msg.params.free_ctx_header;
         int err;
 
-        if (ctx->mem.gpu_va) {
+        if (ctxheader->gpu_va) {
                 msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER;
                 msg.handle = vgpu_get_handle(c->g);
                 p->ch_handle = c->virt_ctx;
@@ -74,8 +74,8 @@ void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c)
                 err = err ? err : msg.ret;
                 if (unlikely(err))
                         nvgpu_err(c->g, "free ctx_header failed err %d", err);
-                __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va,
+                __nvgpu_vm_free_va(c->vm, ctxheader->gpu_va,
                                 GMMU_PAGE_SIZE_KERNEL);
-                ctx->mem.gpu_va = 0;
+                ctxheader->gpu_va = 0;
         }
 }