gpu: nvgpu: add resume_all_sms gr ops

This is required to support multiple SM and t19x
sm register address changes

JIRA GPUT19X-75

Change-Id: I844b5cf02a75ba397891a1100d917875e5a3e181
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512217
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

5 files changed, 7 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index aae54cc2..7dd4a9fa 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -377,6 +377,7 @@ struct gpu_ops {
                                 u32 global_esr_mask, bool check_errors);
                 void (*resume_single_sm)(struct gk20a *g,
                                 u32 gpc, u32 tpc, u32 sm);
+                void (*resume_all_sms)(struct gk20a *g);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 70abef78..42a807f6 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8123,7 +8123,7 @@ void gk20a_gr_resume_single_sm(struct gk20a *g,
                 gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0);
 }
 
-void gk20a_resume_all_sms(struct gk20a *g)
+void gk20a_gr_resume_all_sms(struct gk20a *g)
 {
         u32 dbgr_control0;
         /*
@@ -8236,7 +8236,7 @@ bool gr_gk20a_resume_context(struct channel_gk20a *ch)
         bool ctx_resident = false;
 
         if (gk20a_is_channel_ctx_resident(ch)) {
-                gk20a_resume_all_sms(g);
+                g->ops.gr.resume_all_sms(g);
                 ctx_resident = true;
         } else {
                 gk20a_enable_channel_tsg(g, ch);
@@ -8438,7 +8438,7 @@ int gr_gk20a_resume_from_pause(struct gk20a *g)
 
         /* Now resume all sms, write a 0 to the stop trigger
          * then a 1 to the run trigger */
-        gk20a_resume_all_sms(g);
+        g->ops.gr.resume_all_sms(g);
 
         return err;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 659b37a6..5a28deea 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -614,7 +614,7 @@ int gr_gk20a_disable_ctxsw(struct gk20a *g);
 int gr_gk20a_enable_ctxsw(struct gk20a *g);
 void gk20a_gr_resume_single_sm(struct gk20a *g,
                 u32 gpc, u32 tpc, u32 sm);
-void gk20a_resume_all_sms(struct gk20a *g);
+void gk20a_gr_resume_all_sms(struct gk20a *g);
 void gk20a_gr_suspend_single_sm(struct gk20a *g,
                 u32 gpc, u32 tpc, u32 sm,
                 u32 global_esr_mask, bool check_errors);
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 04c8824b..5fac9ac8 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1634,4 +1634,5 @@ void gm20b_init_gr(struct gpu_ops *gops)
         gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm;
         gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms;
         gops->gr.resume_single_sm = gk20a_gr_resume_single_sm;
+        gops->gr.resume_all_sms = gk20a_gr_resume_all_sms;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index a1be22df..e3ea4603 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -2000,7 +2000,7 @@ static bool gr_gp10b_suspend_context(struct channel_gk20a *ch,
                         else
                                 *cilp_preempt_pending = true;
 
-                        gk20a_resume_all_sms(g);
+                        g->ops.gr.resume_all_sms(g);
                 }
 
                 ctx_resident = true;