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author | Seema Khowala <seemaj@nvidia.com> | 2017-06-30 17:07:38 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-02 13:20:08 -0400 |
commit | 5a57be6ba1d491b4a3258281c82345fdb4a83675 (patch) | |
tree | 9f51cc2af314b0cd06de66b65effe4dd8ecd5848 /drivers | |
parent | f525ff15c4e8b5994201585ad584237b62bf3083 (diff) |
gpu: nvgpu: gv11b: init get_num_pce ce ops
Implement get_num_pce ce ops to get number of physical
copy engines. This is required to calculate eng method
buffer size
JIRA GPUT19X-46
Change-Id: I5a37eb26ec11bc358700d1761cfdb6ca060e4287
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1511788
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/ce_gv11b.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c index 1ba009bd..0bbd05b6 100644 --- a/drivers/gpu/nvgpu/gv11b/ce_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/ce_gv11b.c | |||
@@ -17,6 +17,7 @@ | |||
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include "nvgpu/log.h" | 19 | #include "nvgpu/log.h" |
20 | #include "nvgpu/bitops.h" | ||
20 | 21 | ||
21 | #include "gk20a/gk20a.h" | 22 | #include "gk20a/gk20a.h" |
22 | 23 | ||
@@ -26,6 +27,19 @@ | |||
26 | 27 | ||
27 | #include <nvgpu/hw/gv11b/hw_ce_gv11b.h> | 28 | #include <nvgpu/hw/gv11b/hw_ce_gv11b.h> |
28 | 29 | ||
30 | static u32 gv11b_ce_get_num_pce(struct gk20a *g) | ||
31 | { | ||
32 | /* register contains a bitmask indicating which physical copy | ||
33 | * engines are present (and not floorswept). | ||
34 | */ | ||
35 | u32 num_pce; | ||
36 | u32 ce_pce_map = gk20a_readl(g, ce_pce_map_r()); | ||
37 | |||
38 | num_pce = get_count_order(ce_pce_map) + 1; | ||
39 | nvgpu_log_info(g, "num PCE: %d", num_pce); | ||
40 | return num_pce; | ||
41 | } | ||
42 | |||
29 | static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | 43 | static void gv11b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) |
30 | { | 44 | { |
31 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | 45 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); |
@@ -64,4 +78,5 @@ void gv11b_init_ce(struct gpu_ops *gops) | |||
64 | { | 78 | { |
65 | gp10b_init_ce(gops); | 79 | gp10b_init_ce(gops); |
66 | gops->ce2.isr_stall = gv11b_ce_isr; | 80 | gops->ce2.isr_stall = gv11b_ce_isr; |
81 | gops->ce2.get_num_pce = gv11b_ce_get_num_pce; | ||
67 | } | 82 | } |