gpu: nvgpu: add conversion function for clk domain

Add a conversion function for NVGPU_GPU_CLK_DOMAIN_*
defines present in uapi header.
This enables movement of related code to the OS agnostic
clk_arb.c

Jira VQRM-3741

Change-Id: I922d1cfb91d6a5dda644cf418f2f3815d975fcfd
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709653
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 172 insertions, 153 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c
index eaf9d8a5..8b499b16 100644
--- a/drivers/gpu/nvgpu/clk/clk_arb.c
+++ b/drivers/gpu/nvgpu/clk/clk_arb.c
@@ -1525,3 +1525,131 @@ void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock)
         else
                 nvgpu_mutex_release(&arb->pstate_lock);
 }
+
+bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain)
+{
+        u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g);
+
+        switch (api_domain) {
+        case NVGPU_CLK_DOMAIN_MCLK:
+                return (clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0;
+
+        case NVGPU_CLK_DOMAIN_GPCCLK:
+                return (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0;
+
+        default:
+                return false;
+        }
+}
+
+int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+                u16 *min_mhz, u16 *max_mhz)
+{
+        int ret;
+
+        switch (api_domain) {
+        case NVGPU_CLK_DOMAIN_MCLK:
+                ret = g->ops.clk_arb.get_arbiter_clk_range(g,
+                                CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz);
+                return ret;
+
+        case NVGPU_CLK_DOMAIN_GPCCLK:
+                ret = g->ops.clk_arb.get_arbiter_clk_range(g,
+                                CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz);
+                if (!ret) {
+                        *min_mhz /= 2;
+                        *max_mhz /= 2;
+                }
+                return ret;
+
+        default:
+                return -EINVAL;
+        }
+}
+
+int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
+        u32 api_domain, u32 *max_points, u16 *fpoints)
+{
+        int err;
+        u32 i;
+
+        switch (api_domain) {
+        case NVGPU_CLK_DOMAIN_GPCCLK:
+                err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK,
+                                max_points, fpoints);
+                if (err || !fpoints)
+                        return err;
+                for (i = 0; i < *max_points; i++)
+                        fpoints[i] /= 2;
+                return 0;
+        case NVGPU_CLK_DOMAIN_MCLK:
+                return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK,
+                                max_points, fpoints);
+        default:
+                return -EINVAL;
+        }
+}
+
+int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
+                u32 api_domain, u16 *freq_mhz)
+{
+        int err = 0;
+        struct nvgpu_clk_arb_target *target = session->target;
+
+        switch (api_domain) {
+                case NVGPU_CLK_DOMAIN_MCLK:
+                        *freq_mhz = target->mclk;
+                        break;
+
+                case NVGPU_CLK_DOMAIN_GPCCLK:
+                        *freq_mhz = target->gpc2clk / 2ULL;
+                        break;
+
+                default:
+                        *freq_mhz = 0;
+                        err = -EINVAL;
+        }
+        return err;
+}
+
+int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
+                u32 api_domain, u16 *freq_mhz)
+{
+        struct nvgpu_clk_arb *arb = g->clk_arb;
+        int err = 0;
+        struct nvgpu_clk_arb_target *actual = arb->actual;
+
+        switch (api_domain) {
+                case NVGPU_CLK_DOMAIN_MCLK:
+                        *freq_mhz = actual->mclk;
+                        break;
+
+                case NVGPU_CLK_DOMAIN_GPCCLK:
+                        *freq_mhz = actual->gpc2clk / 2ULL;
+                        break;
+
+                default:
+                        *freq_mhz = 0;
+                        err = -EINVAL;
+        }
+        return err;
+}
+
+int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
+                u32 api_domain, u16 *freq_mhz)
+{
+        switch (api_domain) {
+        case NVGPU_CLK_DOMAIN_MCLK:
+                *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) /
+                        1000000ULL;
+                return 0;
+
+        case NVGPU_CLK_DOMAIN_GPCCLK:
+                *freq_mhz = g->ops.clk.measure_freq(g,
+                        CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL;
+                return 0;
+
+        default:
+                return -EINVAL;
+        }
+}
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
index 9593e2b7..09d47722 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c
@@ -457,11 +457,11 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
         }
 
         switch (api_domain) {
-        case NVGPU_GPU_CLK_DOMAIN_MCLK:
+        case NVGPU_CLK_DOMAIN_MCLK:
                 dev->mclk_target_mhz = target_mhz;
                 break;
 
-        case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
+        case NVGPU_CLK_DOMAIN_GPCCLK:
                 dev->gpc2clk_target_mhz = target_mhz * 2ULL;
                 break;
 
@@ -474,107 +474,6 @@ fdput_fd:
         return err;
 }
 
-int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
-                u32 api_domain, u16 *freq_mhz)
-{
-        int err = 0;
-        struct nvgpu_clk_arb_target *target;
-
-        do {
-                target = NV_ACCESS_ONCE(session->target);
-                /* no reordering of this pointer */
-                nvgpu_smp_rmb();
-
-                switch (api_domain) {
-                case NVGPU_GPU_CLK_DOMAIN_MCLK:
-                        *freq_mhz = target->mclk;
-                        break;
-
-                case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
-                        *freq_mhz = target->gpc2clk / 2ULL;
-                        break;
-
-                default:
-                        *freq_mhz = 0;
-                        err = -EINVAL;
-                }
-        } while (target != NV_ACCESS_ONCE(session->target));
-        return err;
-}
-
-int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
-                u32 api_domain, u16 *freq_mhz)
-{
-        struct nvgpu_clk_arb *arb = g->clk_arb;
-        int err = 0;
-        struct nvgpu_clk_arb_target *actual;
-
-        do {
-                actual = NV_ACCESS_ONCE(arb->actual);
-                /* no reordering of this pointer */
-                nvgpu_smp_rmb();
-
-                switch (api_domain) {
-                case NVGPU_GPU_CLK_DOMAIN_MCLK:
-                        *freq_mhz = actual->mclk;
-                        break;
-
-                case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
-                        *freq_mhz = actual->gpc2clk / 2ULL;
-                        break;
-
-                default:
-                        *freq_mhz = 0;
-                        err = -EINVAL;
-                }
-        } while (actual != NV_ACCESS_ONCE(arb->actual));
-        return err;
-}
-
-int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
-                u32 api_domain, u16 *freq_mhz)
-{
-        switch (api_domain) {
-        case NVGPU_GPU_CLK_DOMAIN_MCLK:
-                *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) /
-                        1000000ULL;
-                return 0;
-
-        case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
-                *freq_mhz = g->ops.clk.measure_freq(g,
-                        CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL;
-                return 0;
-
-        default:
-                return -EINVAL;
-        }
-}
-
-int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
-                u16 *min_mhz, u16 *max_mhz)
-{
-        int ret;
-
-        switch (api_domain) {
-        case NVGPU_GPU_CLK_DOMAIN_MCLK:
-                ret = g->ops.clk_arb.get_arbiter_clk_range(g,
-                                CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz);
-                return ret;
-
-        case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
-                ret = g->ops.clk_arb.get_arbiter_clk_range(g,
-                                CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz);
-                if (!ret) {
-                        *min_mhz /= 2;
-                        *max_mhz /= 2;
-                }
-                return ret;
-
-        default:
-                return -EINVAL;
-        }
-}
-
 u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
 {
         u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g);
@@ -589,45 +488,6 @@ u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
         return api_domains;
 }
 
-bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain)
-{
-        u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g);
-
-        switch (api_domain) {
-        case NVGPU_GPU_CLK_DOMAIN_MCLK:
-                return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0);
-
-        case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
-                return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0);
-
-        default:
-                return false;
-        }
-}
-
-int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
-        u32 api_domain, u32 *max_points, u16 *fpoints)
-{
-        int err;
-        u32 i;
-
-        switch (api_domain) {
-        case NVGPU_GPU_CLK_DOMAIN_GPCCLK:
-                err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK,
-                                max_points, fpoints);
-                if (err || !fpoints)
-                        return err;
-                for (i = 0; i < *max_points; i++)
-                        fpoints[i] /= 2;
-                return 0;
-        case NVGPU_GPU_CLK_DOMAIN_MCLK:
-                return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK,
-                                max_points, fpoints);
-        default:
-                return -EINVAL;
-        }
-}
-
 #ifdef CONFIG_DEBUG_FS
 static int nvgpu_clk_arb_stats_show(struct seq_file *s, void *unused)
 {
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
index e7da0978..b40efc0f 100644
--- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c
@@ -968,6 +968,20 @@ static int nvgpu_gpu_get_memory_state(struct gk20a *g,
         return err;
 }
 
+static u32 nvgpu_gpu_convert_clk_domain(u32 clk_domain)
+{
+        u32 domain = 0;
+
+        if (clk_domain == NVGPU_GPU_CLK_DOMAIN_MCLK)
+                domain = NVGPU_CLK_DOMAIN_MCLK;
+        else if (clk_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK)
+                domain = NVGPU_CLK_DOMAIN_GPCCLK;
+        else
+                domain = NVGPU_CLK_DOMAIN_MAX + 1;
+
+        return domain;
+}
+
 static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g,
                 struct gk20a_ctrl_priv *priv,
                 struct nvgpu_gpu_clk_vf_points_args *args)
@@ -993,11 +1007,13 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g,
         clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g);
         args->num_entries = 0;
 
-        if (!nvgpu_clk_arb_is_valid_domain(g, args->clk_domain))
+        if (!nvgpu_clk_arb_is_valid_domain(g,
+                                nvgpu_gpu_convert_clk_domain(args->clk_domain)))
                 return -EINVAL;
 
         err = nvgpu_clk_arb_get_arbiter_clk_f_points(g,
-                        args->clk_domain, &max_points, NULL);
+                        nvgpu_gpu_convert_clk_domain(args->clk_domain),
+                        &max_points, NULL);
         if (err)
                 return err;
 
@@ -1009,7 +1025,8 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g,
         if (args->max_entries < max_points)
                 return -EINVAL;
 
-        err = nvgpu_clk_arb_get_arbiter_clk_range(g, args->clk_domain,
+        err = nvgpu_clk_arb_get_arbiter_clk_range(g,
+                        nvgpu_gpu_convert_clk_domain(args->clk_domain),
                         &min_mhz, &max_mhz);
         if (err)
                 return err;
@@ -1019,7 +1036,8 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g,
                 return -ENOMEM;
 
         err = nvgpu_clk_arb_get_arbiter_clk_f_points(g,
-                        args->clk_domain, &max_points, fpoints);
+                        nvgpu_gpu_convert_clk_domain(args->clk_domain),
+                        &max_points, fpoints);
         if (err)
                 goto fail;
 
@@ -1117,7 +1135,7 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g,
 
                 clk_range.flags = 0;
                 err = nvgpu_clk_arb_get_arbiter_clk_range(g,
-                                clk_range.clk_domain,
+                                nvgpu_gpu_convert_clk_domain(clk_range.clk_domain),
                                 &min_mhz, &max_mhz);
                 clk_range.min_hz = MHZ_TO_HZ(min_mhz);
                 clk_range.max_hz = MHZ_TO_HZ(max_mhz);
@@ -1135,7 +1153,6 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g,
         return 0;
 }
 
-
 static int nvgpu_gpu_clk_set_info(struct gk20a *g,
                 struct gk20a_ctrl_priv *priv,
                 struct nvgpu_gpu_clk_set_info_args *args)
@@ -1167,7 +1184,8 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g,
                 if (copy_from_user(&clk_info, entry, sizeof(clk_info)))
                         return -EFAULT;
 
-                if (!nvgpu_clk_arb_is_valid_domain(g, clk_info.clk_domain))
+                if (!nvgpu_clk_arb_is_valid_domain(g,
+                                        nvgpu_gpu_convert_clk_domain(clk_info.clk_domain)))
                         return -EINVAL;
         }
 
@@ -1186,7 +1204,7 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g,
                 freq_mhz = HZ_TO_MHZ(clk_info.freq_hz);
 
                 nvgpu_clk_arb_set_session_target_mhz(session, fd,
-                                clk_info.clk_domain, freq_mhz);
+                                nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), freq_mhz);
         }
 
         ret = nvgpu_clk_arb_commit_request_fd(g, session, fd);
@@ -1261,15 +1279,18 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g,
                 switch (clk_info.clk_type) {
                 case NVGPU_GPU_CLK_TYPE_TARGET:
                         err = nvgpu_clk_arb_get_session_target_mhz(session,
-                                        clk_info.clk_domain, &freq_mhz);
+                                        nvgpu_gpu_convert_clk_domain(clk_info.clk_domain),
+                                        &freq_mhz);
                         break;
                 case NVGPU_GPU_CLK_TYPE_ACTUAL:
                         err = nvgpu_clk_arb_get_arbiter_actual_mhz(g,
-                                        clk_info.clk_domain, &freq_mhz);
+                                        nvgpu_gpu_convert_clk_domain(clk_info.clk_domain),
+                                        &freq_mhz);
                         break;
                 case NVGPU_GPU_CLK_TYPE_EFFECTIVE:
                         err = nvgpu_clk_arb_get_arbiter_effective_mhz(g,
-                                        clk_info.clk_domain, &freq_mhz);
+                                        nvgpu_gpu_convert_clk_domain(clk_info.clk_domain),
+                                        &freq_mhz);
                         break;
                 default:
                         freq_mhz = 0;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
index 06136c02..e91a0dad 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h
@@ -102,6 +102,16 @@ struct nvgpu_clk_session;
 #define NVGPU_POLLRDNORM (1 << 3)
 #define NVGPU_POLLHUP (1 << 4)
 
+/* NVGPU_CLK_DOMAIN_* defines equivalent to NVGPU_GPU_CLK_DOMAIN_*
+ * defines in uapi header
+ */
+/* Memory clock */
+#define NVGPU_CLK_DOMAIN_MCLK   (0)
+/* Main graphics core clock */
+#define NVGPU_CLK_DOMAIN_GPCCLK (1)
+
+#define NVGPU_CLK_DOMAIN_MAX    (NVGPU_CLK_DOMAIN_GPCCLK)
+
 #define clk_arb_dbg(g, fmt, args...)    \
         do {                                                            \
                 nvgpu_log(g, gpu_dbg_clk_arb,   \