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authorVijayakumar Subbu <vsubbu@nvidia.com>2016-07-28 01:30:37 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-09-08 23:06:06 -0400
commit589179ad00b78485a071131b5f08c874e8b3ef84 (patch)
tree58288ecae1d2492b5916840ccdd6844a6e3049f8 /drivers
parent7d44a8d8d8884e92f02dfdc6efe8e3a59b69c28f (diff)
gpu: nvgpu: refactor pmu include
split pmu include files to add lot more APIs pmu_api.h - all the current APIs used in igpu pmu_common.h - common defines for all APIs pmu_gk20a.h - SW defines specific needed for nvgpu like PMU version, PMU SW structure definition etc. Splitting APIs to separate files allows us to use auto generated PMU task headers from RM We have script which generates pmu interface herader files in linux format. It replaces RM with NV. Adding typedef in existing pmu code make auto generated files easy to compile/add JIRA DNVGPU-85 Change-Id: I851b88769fe8d60561a44754ddb7dde45b45959e Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1192702 Reviewed-on: http://git-master/r/1203124 (cherry picked from commit 0fe5f020c3f934cf2cc5336f1b6c3bafaf9e0c2a) Reviewed-on: http://git-master/r/1217301 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_api.h664
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_common.h145
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h766
3 files changed, 812 insertions, 763 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_api.h b/drivers/gpu/nvgpu/gk20a/pmu_api.h
new file mode 100644
index 00000000..aa10661c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/pmu_api.h
@@ -0,0 +1,664 @@
1/*
2 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __PMU_API_H__
15#define __PMU_API_H__
16
17#include "pmu_common.h"
18
19/* PMU Command/Message Interfaces for Adaptive Power */
20/* Macro to get Histogram index */
21#define PMU_AP_HISTOGRAM(idx) (idx)
22#define PMU_AP_HISTOGRAM_CONT (4)
23
24/* Total number of histogram bins */
25#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
26
27/* Mapping between Idle counters and histograms */
28#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
29#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
30#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
31#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
32
33
34/* Mapping between AP_CTRLs and Histograms */
35#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
36
37/* Mapping between AP_CTRLs and Idle counters */
38#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
39
40/* Adaptive Power Controls (AP_CTRL) */
41enum {
42 PMU_AP_CTRL_ID_GRAPHICS = 0x0,
43 PMU_AP_CTRL_ID_MAX,
44};
45
46/* AP_CTRL Statistics */
47struct pmu_ap_ctrl_stat {
48 /*
49 * Represents whether AP is active or not
50 */
51 u8 b_active;
52
53 /* Idle filter represented by histogram bin index */
54 u8 idle_filter_x;
55 u8 rsvd[2];
56
57 /* Total predicted power saving cycles. */
58 s32 power_saving_h_cycles;
59
60 /* Counts how many times AP gave us -ve power benefits. */
61 u32 bad_decision_count;
62
63 /*
64 * Number of times ap structure needs to skip AP iterations
65 * KICK_CTRL from kernel updates this parameter.
66 */
67 u32 skip_count;
68 u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
69};
70
71/* Parameters initialized by INITn APCTRL command */
72struct pmu_ap_ctrl_init_params {
73 /* Minimum idle filter value in Us */
74 u32 min_idle_filter_us;
75
76 /*
77 * Minimum Targeted Saving in Us. AP will update idle thresholds only
78 * if power saving achieved by updating idle thresholds is greater than
79 * Minimum targeted saving.
80 */
81 u32 min_target_saving_us;
82
83 /* Minimum targeted residency of power feature in Us */
84 u32 power_break_even_us;
85
86 /*
87 * Maximum number of allowed power feature cycles per sample.
88 *
89 * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
90 * AKA pgPerSampleMax in original algorithm.
91 */
92 u32 cycles_per_sample_max;
93};
94
95/* AP Commands/Message structures */
96
97/*
98 * Structure for Generic AP Commands
99 */
100struct pmu_ap_cmd_common {
101 u8 cmd_type;
102 u16 cmd_id;
103};
104
105/*
106 * Structure for INIT AP command
107 */
108struct pmu_ap_cmd_init {
109 u8 cmd_type;
110 u16 cmd_id;
111 u8 rsvd;
112 u32 pg_sampling_period_us;
113};
114
115/*
116 * Structure for Enable/Disable ApCtrl Commands
117 */
118struct pmu_ap_cmd_enable_ctrl {
119 u8 cmd_type;
120 u16 cmd_id;
121
122 u8 ctrl_id;
123};
124
125struct pmu_ap_cmd_disable_ctrl {
126 u8 cmd_type;
127 u16 cmd_id;
128
129 u8 ctrl_id;
130};
131
132/*
133 * Structure for INIT command
134 */
135struct pmu_ap_cmd_init_ctrl {
136 u8 cmd_type;
137 u16 cmd_id;
138 u8 ctrl_id;
139 struct pmu_ap_ctrl_init_params params;
140};
141
142struct pmu_ap_cmd_init_and_enable_ctrl {
143 u8 cmd_type;
144 u16 cmd_id;
145 u8 ctrl_id;
146 struct pmu_ap_ctrl_init_params params;
147};
148
149/*
150 * Structure for KICK_CTRL command
151 */
152struct pmu_ap_cmd_kick_ctrl {
153 u8 cmd_type;
154 u16 cmd_id;
155 u8 ctrl_id;
156
157 u32 skip_count;
158};
159
160/*
161 * Structure for PARAM command
162 */
163struct pmu_ap_cmd_param {
164 u8 cmd_type;
165 u16 cmd_id;
166 u8 ctrl_id;
167
168 u32 data;
169};
170
171/*
172 * Defines for AP commands
173 */
174enum {
175 PMU_AP_CMD_ID_INIT = 0x0,
176 PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
177 PMU_AP_CMD_ID_ENABLE_CTRL,
178 PMU_AP_CMD_ID_DISABLE_CTRL,
179 PMU_AP_CMD_ID_KICK_CTRL,
180};
181
182/*
183 * AP Command
184 */
185union pmu_ap_cmd {
186 u8 cmd_type;
187 struct pmu_ap_cmd_common cmn;
188 struct pmu_ap_cmd_init init;
189 struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
190 struct pmu_ap_cmd_enable_ctrl enable_ctrl;
191 struct pmu_ap_cmd_disable_ctrl disable_ctrl;
192 struct pmu_ap_cmd_kick_ctrl kick_ctrl;
193};
194
195/*
196 * Structure for generic AP Message
197 */
198struct pmu_ap_msg_common {
199 u8 msg_type;
200 u16 msg_id;
201};
202
203/*
204 * Structure for INIT_ACK Message
205 */
206struct pmu_ap_msg_init_ack {
207 u8 msg_type;
208 u16 msg_id;
209 u8 ctrl_id;
210 u32 stats_dmem_offset;
211};
212
213/*
214 * Defines for AP messages
215 */
216enum {
217 PMU_AP_MSG_ID_INIT_ACK = 0x0,
218};
219
220/*
221 * AP Message
222 */
223union pmu_ap_msg {
224 u8 msg_type;
225 struct pmu_ap_msg_common cmn;
226 struct pmu_ap_msg_init_ack init_ack;
227};
228
229/* Default Sampling Period of AELPG */
230#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
231
232/* Default values of APCTRL parameters */
233#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
234#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
235#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
236#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
237
238/*
239 * Disable reason for Adaptive Power Controller
240 */
241enum {
242 APCTRL_DISABLE_REASON_RM_UNLOAD,
243 APCTRL_DISABLE_REASON_RMCTRL,
244};
245
246/*
247 * Adaptive Power Controller
248 */
249struct ap_ctrl {
250 u32 stats_dmem_offset;
251 u32 disable_reason_mask;
252 struct pmu_ap_ctrl_stat stat_cache;
253 u8 b_ready;
254};
255
256/*
257 * Adaptive Power structure
258 *
259 * ap structure provides generic infrastructure to make any power feature
260 * adaptive.
261 */
262struct pmu_ap {
263 u32 supported_mask;
264 struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
265};
266/*---------------------------------------------------------*/
267
268/*perfmon task defines*/
269enum pmu_perfmon_cmd_start_fields {
270 COUNTER_ALLOC
271};
272
273enum {
274 PMU_PERFMON_CMD_ID_START = 0,
275 PMU_PERFMON_CMD_ID_STOP = 1,
276 PMU_PERFMON_CMD_ID_INIT = 2
277};
278
279struct pmu_perfmon_cmd_start_v3 {
280 u8 cmd_type;
281 u8 group_id;
282 u8 state_id;
283 u8 flags;
284 struct pmu_allocation_v3 counter_alloc;
285};
286
287struct pmu_perfmon_cmd_start_v2 {
288 u8 cmd_type;
289 u8 group_id;
290 u8 state_id;
291 u8 flags;
292 struct pmu_allocation_v2 counter_alloc;
293};
294
295struct pmu_perfmon_cmd_start_v1 {
296 u8 cmd_type;
297 u8 group_id;
298 u8 state_id;
299 u8 flags;
300 struct pmu_allocation_v1 counter_alloc;
301};
302
303struct pmu_perfmon_cmd_start_v0 {
304 u8 cmd_type;
305 u8 group_id;
306 u8 state_id;
307 u8 flags;
308 struct pmu_allocation_v0 counter_alloc;
309};
310
311struct pmu_perfmon_cmd_stop {
312 u8 cmd_type;
313};
314
315struct pmu_perfmon_cmd_init_v3 {
316 u8 cmd_type;
317 u8 to_decrease_count;
318 u8 base_counter_id;
319 u32 sample_period_us;
320 struct pmu_allocation_v3 counter_alloc;
321 u8 num_counters;
322 u8 samples_in_moving_avg;
323 u16 sample_buffer;
324};
325
326struct pmu_perfmon_cmd_init_v2 {
327 u8 cmd_type;
328 u8 to_decrease_count;
329 u8 base_counter_id;
330 u32 sample_period_us;
331 struct pmu_allocation_v2 counter_alloc;
332 u8 num_counters;
333 u8 samples_in_moving_avg;
334 u16 sample_buffer;
335};
336
337struct pmu_perfmon_cmd_init_v1 {
338 u8 cmd_type;
339 u8 to_decrease_count;
340 u8 base_counter_id;
341 u32 sample_period_us;
342 struct pmu_allocation_v1 counter_alloc;
343 u8 num_counters;
344 u8 samples_in_moving_avg;
345 u16 sample_buffer;
346};
347
348struct pmu_perfmon_cmd_init_v0 {
349 u8 cmd_type;
350 u8 to_decrease_count;
351 u8 base_counter_id;
352 u32 sample_period_us;
353 struct pmu_allocation_v0 counter_alloc;
354 u8 num_counters;
355 u8 samples_in_moving_avg;
356 u16 sample_buffer;
357};
358
359struct pmu_perfmon_cmd {
360 union {
361 u8 cmd_type;
362 struct pmu_perfmon_cmd_start_v0 start_v0;
363 struct pmu_perfmon_cmd_start_v1 start_v1;
364 struct pmu_perfmon_cmd_start_v2 start_v2;
365 struct pmu_perfmon_cmd_start_v3 start_v3;
366 struct pmu_perfmon_cmd_stop stop;
367 struct pmu_perfmon_cmd_init_v0 init_v0;
368 struct pmu_perfmon_cmd_init_v1 init_v1;
369 struct pmu_perfmon_cmd_init_v2 init_v2;
370 struct pmu_perfmon_cmd_init_v3 init_v3;
371 };
372};
373
374struct pmu_zbc_cmd {
375 u8 cmd_type;
376 u8 pad;
377 u16 entry_mask;
378};
379
380/* PERFMON MSG */
381enum {
382 PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
383 PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
384 PMU_PERFMON_MSG_ID_INIT_EVENT = 2,
385 PMU_PERFMON_MSG_ID_ACK = 3
386};
387
388struct pmu_perfmon_msg_generic {
389 u8 msg_type;
390 u8 state_id;
391 u8 group_id;
392 u8 data;
393};
394
395struct pmu_perfmon_msg {
396 union {
397 u8 msg_type;
398 struct pmu_perfmon_msg_generic gen;
399 };
400};
401/*---------------------------------------------------------*/
402/*ELPG/PG defines*/
403enum {
404 PMU_PG_ELPG_MSG_INIT_ACK,
405 PMU_PG_ELPG_MSG_DISALLOW_ACK,
406 PMU_PG_ELPG_MSG_ALLOW_ACK,
407 PMU_PG_ELPG_MSG_FREEZE_ACK,
408 PMU_PG_ELPG_MSG_FREEZE_ABORT,
409 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
410};
411
412struct pmu_pg_msg_elpg_msg {
413 u8 msg_type;
414 u8 engine_id;
415 u16 msg;
416};
417
418enum {
419 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
420};
421
422struct pmu_pg_msg_stat {
423 u8 msg_type;
424 u8 engine_id;
425 u16 sub_msg_id;
426 u32 data;
427};
428
429enum {
430 PMU_PG_MSG_ENG_BUF_LOADED,
431 PMU_PG_MSG_ENG_BUF_UNLOADED,
432 PMU_PG_MSG_ENG_BUF_FAILED,
433};
434
435struct pmu_pg_msg_eng_buf_stat {
436 u8 msg_type;
437 u8 engine_id;
438 u8 buf_idx;
439 u8 status;
440};
441
442struct pmu_pg_msg {
443 union {
444 u8 msg_type;
445 struct pmu_pg_msg_elpg_msg elpg_msg;
446 struct pmu_pg_msg_stat stat;
447 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
448 /* TBD: other pg messages */
449 union pmu_ap_msg ap_msg;
450 };
451};
452
453enum {
454 PMU_PG_ELPG_CMD_INIT,
455 PMU_PG_ELPG_CMD_DISALLOW,
456 PMU_PG_ELPG_CMD_ALLOW,
457 PMU_PG_ELPG_CMD_FREEZE,
458 PMU_PG_ELPG_CMD_UNFREEZE,
459};
460
461struct pmu_pg_cmd_elpg_cmd {
462 u8 cmd_type;
463 u8 engine_id;
464 u16 cmd;
465};
466
467struct pmu_pg_cmd_eng_buf_load_v0 {
468 u8 cmd_type;
469 u8 engine_id;
470 u8 buf_idx;
471 u8 pad;
472 u16 buf_size;
473 u32 dma_base;
474 u8 dma_offset;
475 u8 dma_idx;
476};
477
478struct pmu_pg_cmd_eng_buf_load_v1 {
479 u8 cmd_type;
480 u8 engine_id;
481 u8 buf_idx;
482 u8 pad;
483 struct flcn_mem_desc {
484 struct falc_u64 dma_addr;
485 u16 dma_size;
486 u8 dma_idx;
487 } dma_desc;
488};
489
490struct pmu_pg_cmd_eng_buf_load_v2 {
491 u8 cmd_type;
492 u8 engine_id;
493 u8 buf_idx;
494 u8 pad;
495 struct flcn_mem_desc_v0 dma_desc;
496};
497
498enum {
499 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
500};
501
502#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
503
504#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
505#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
506
507struct pmu_pg_cmd_gr_init_param {
508 u8 cmd_type;
509 u16 sub_cmd_id;
510 u8 featuremask;
511};
512
513struct pmu_pg_cmd_stat {
514 u8 cmd_type;
515 u8 engine_id;
516 u16 sub_cmd_id;
517 u32 data;
518};
519
520struct pmu_pg_cmd {
521 union {
522 u8 cmd_type;
523 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
524 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
525 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
526 struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
527 struct pmu_pg_cmd_stat stat;
528 struct pmu_pg_cmd_gr_init_param gr_init_param;
529 /* TBD: other pg commands */
530 union pmu_ap_cmd ap_cmd;
531 };
532};
533
534/*---------------------------------------------------------*/
535/* ACR Commands/Message structures */
536
537enum {
538 PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0,
539 PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
540 PMU_ACR_CMD_ID_RESERVED,
541 PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS,
542};
543
544/*
545 * Initializes the WPR region details
546 */
547struct pmu_acr_cmd_init_wpr_details {
548 u8 cmd_type;
549 u32 regionid;
550 u32 wproffset;
551
552};
553
554/*
555 * falcon ID to bootstrap
556 */
557struct pmu_acr_cmd_bootstrap_falcon {
558 u8 cmd_type;
559 u32 flags;
560 u32 falconid;
561};
562
563/*
564 * falcon ID to bootstrap
565 */
566struct pmu_acr_cmd_bootstrap_multiple_falcons {
567 u8 cmd_type;
568 u32 flags;
569 u32 falconidmask;
570 u32 usevamask;
571 struct falc_u64 wprvirtualbase;
572};
573
574#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1
575#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0
576
577
578struct pmu_acr_cmd {
579 union {
580 u8 cmd_type;
581 struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon;
582 struct pmu_acr_cmd_init_wpr_details init_wpr;
583 struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons;
584 };
585};
586
587/* acr messages */
588
589/*
590 * returns the WPR region init information
591 */
592#define PMU_ACR_MSG_ID_INIT_WPR_REGION 0
593
594/*
595 * Returns the Bootstrapped falcon ID to RM
596 */
597#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1
598
599/*
600 * Returns the WPR init status
601 */
602#define PMU_ACR_SUCCESS 0
603#define PMU_ACR_ERROR 1
604
605/*
606 * PMU notifies about bootstrap status of falcon
607 */
608struct pmu_acr_msg_bootstrap_falcon {
609 u8 msg_type;
610 union {
611 u32 errorcode;
612 u32 falconid;
613 };
614};
615
616struct pmu_acr_msg {
617 union {
618 u8 msg_type;
619 struct pmu_acr_msg_bootstrap_falcon acrmsg;
620 };
621};
622/*---------------------------------------------------------*/
623/* FECS mem override command*/
624
625#define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0
626
627/*!
628 * Enable/Disable FECS error feature
629 */
630struct pmu_cmd_lrf_tex_ltc_dram_en_dis {
631 /*Command type must be first*/
632 u8 cmd_type;
633 /*unit bitmask*/
634 u8 en_dis_mask;
635};
636
637struct pmu_lrf_tex_ltc_dram_cmd {
638 union {
639 u8 cmd_type;
640 struct pmu_cmd_lrf_tex_ltc_dram_en_dis en_dis;
641 };
642};
643
644/* FECS mem override messages*/
645#define PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS 0
646
647struct pmu_msg_lrf_tex_ltc_dram_en_dis {
648 /*!
649 * Must be at start
650 */
651 u8 msg_type;
652 u8 en_fail_mask;
653 u8 dis_fail_mask;
654 u32 pmu_status;
655};
656
657struct pmu_lrf_tex_ltc_dram_msg {
658 union {
659 u8 msg_type;
660 struct pmu_msg_lrf_tex_ltc_dram_en_dis en_dis;
661 };
662};
663
664#endif /*__PMU_API_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_common.h b/drivers/gpu/nvgpu/gk20a/pmu_common.h
new file mode 100644
index 00000000..76b37cf7
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/pmu_common.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef __PMU_COMMON_H__
15#define __PMU_COMMON_H__
16
17#define PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED 0
18
19struct falc_u64 {
20 u32 lo;
21 u32 hi;
22};
23
24struct falc_dma_addr {
25 u32 dma_base;
26 /*
27 * dma_base1 is 9-bit MSB for FB Base
28 * address for the transfer in FB after
29 * address using 49b FB address
30 */
31 u16 dma_base1;
32 u8 dma_offset;
33};
34
35struct pmu_mem_v0 {
36 u32 dma_base;
37 u8 dma_offset;
38 u8 dma_idx;
39};
40
41struct pmu_mem_v1 {
42 u32 dma_base;
43 u8 dma_offset;
44 u8 dma_idx;
45 u16 fb_size;
46};
47
48struct pmu_mem_v2 {
49 struct falc_dma_addr dma_addr;
50 u8 dma_idx;
51 u16 fb_size;
52};
53
54struct pmu_mem_desc_v0 {
55 /*!
56 * Start address of memory surface that is being communicated to the falcon.
57 */
58 struct falc_u64 dma_addr;
59 /*!
60 * Max allowed DMA transfer size (size of the memory surface). Accesses past
61 * this point may result in page faults and/or memory corruptions.
62 */
63 u16 dma_sizemax;
64 /*!
65 * DMA channel index to be used when accessing this surface.
66 */
67 u8 dma_idx;
68};
69
70struct pmu_dmem {
71 u16 size;
72 u32 offset;
73};
74
75/* Make sure size of this structure is a multiple of 4 bytes */
76struct pmu_cmdline_args_v0 {
77 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
78 u32 falc_trace_size; /* falctrace buffer size (bytes) */
79 u32 falc_trace_dma_base; /* 256-byte block address */
80 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
81 struct pmu_mem_v0 gc6_ctx; /* dmem offset of gc6 context */
82};
83
84struct pmu_cmdline_args_v1 {
85 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
86 u32 falc_trace_size; /* falctrace buffer size (bytes) */
87 u32 falc_trace_dma_base; /* 256-byte block address */
88 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
89 u8 secure_mode;
90 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */
91};
92
93struct flcn_u64 {
94 u32 lo;
95 u32 hi;
96};
97
98struct flcn_mem_desc_v0 {
99 struct flcn_u64 address;
100 u32 params;
101};
102
103#define nv_flcn_mem_desc flcn_mem_desc_v0
104
105struct pmu_allocation_v0 {
106 u8 pad[3];
107 u8 fb_mem_use;
108 struct {
109 struct pmu_dmem dmem;
110 struct pmu_mem_v0 fb;
111 } alloc;
112};
113
114struct pmu_allocation_v1 {
115 struct {
116 struct pmu_dmem dmem;
117 struct pmu_mem_v1 fb;
118 } alloc;
119};
120
121struct pmu_allocation_v2 {
122 struct {
123 struct pmu_dmem dmem;
124 struct pmu_mem_desc_v0 fb;
125 } alloc;
126};
127
128struct pmu_allocation_v3 {
129 struct {
130 struct pmu_dmem dmem;
131 struct flcn_mem_desc_v0 fb;
132 } alloc;
133};
134
135struct pmu_hdr {
136 u8 unit_id;
137 u8 size;
138 u8 ctrl_flags;
139 u8 seq_id;
140};
141
142#define nv_pmu_hdr pmu_hdr
143typedef u8 flcn_status;
144
145#endif /*__PMU_COMMON_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index bbcccdeb..d8af5d7c 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -21,6 +21,9 @@
21#ifndef __PMU_GK20A_H__ 21#ifndef __PMU_GK20A_H__
22#define __PMU_GK20A_H__ 22#define __PMU_GK20A_H__
23 23
24#include "pmu_api.h"
25#include "pmu_common.h"
26
24/* defined by pmu hw spec */ 27/* defined by pmu hw spec */
25#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) 28#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024)
26#define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024) 29#define GK20A_PMU_UCODE_SIZE_MAX (256 * 1024)
@@ -28,27 +31,6 @@
28 31
29#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe) 32#define ZBC_MASK(i) (~(~(0) << ((i)+1)) & 0xfffe)
30 33
31/* PMU Command/Message Interfaces for Adaptive Power */
32/* Macro to get Histogram index */
33#define PMU_AP_HISTOGRAM(idx) (idx)
34#define PMU_AP_HISTOGRAM_CONT (4)
35
36/* Total number of histogram bins */
37#define PMU_AP_CFG_HISTOGRAM_BIN_N (16)
38
39/* Mapping between Idle counters and histograms */
40#define PMU_AP_IDLE_MASK_HIST_IDX_0 (2)
41#define PMU_AP_IDLE_MASK_HIST_IDX_1 (3)
42#define PMU_AP_IDLE_MASK_HIST_IDX_2 (5)
43#define PMU_AP_IDLE_MASK_HIST_IDX_3 (6)
44
45
46/* Mapping between AP_CTRLs and Histograms */
47#define PMU_AP_HISTOGRAM_IDX_GRAPHICS (PMU_AP_HISTOGRAM(1))
48
49/* Mapping between AP_CTRLs and Idle counters */
50#define PMU_AP_IDLE_MASK_GRAPHICS (PMU_AP_IDLE_MASK_HIST_IDX_1)
51
52#define APP_VERSION_NC_2 20429989 34#define APP_VERSION_NC_2 20429989
53#define APP_VERSION_NC_1 20313802 35#define APP_VERSION_NC_1 20313802
54#define APP_VERSION_NC_0 20360931 36#define APP_VERSION_NC_0 20360931
@@ -71,240 +53,6 @@
71#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6 53#define PMU_MODE_MISMATCH_STATUS_MAILBOX_R 6
72#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD 54#define PMU_MODE_MISMATCH_STATUS_VAL 0xDEADDEAD
73 55
74
75enum pmu_perfmon_cmd_start_fields {
76 COUNTER_ALLOC
77};
78
79/* Adaptive Power Controls (AP_CTRL) */
80enum {
81 PMU_AP_CTRL_ID_GRAPHICS = 0x0,
82 /* PMU_AP_CTRL_ID_MS ,*/
83 PMU_AP_CTRL_ID_MAX ,
84};
85
86/* AP_CTRL Statistics */
87struct pmu_ap_ctrl_stat {
88 /*
89 * Represents whether AP is active or not
90 * TODO: This is NvBool in RM; is that 1 byte of 4 bytes?
91 */
92 u8 b_active;
93
94 /* Idle filter represented by histogram bin index */
95 u8 idle_filter_x;
96 u8 rsvd[2];
97
98 /* Total predicted power saving cycles. */
99 s32 power_saving_h_cycles;
100
101 /* Counts how many times AP gave us -ve power benefits. */
102 u32 bad_decision_count;
103
104 /*
105 * Number of times ap structure needs to skip AP iterations
106 * KICK_CTRL from kernel updates this parameter.
107 */
108 u32 skip_count;
109 u8 bin[PMU_AP_CFG_HISTOGRAM_BIN_N];
110};
111
112/* Parameters initialized by INITn APCTRL command */
113struct pmu_ap_ctrl_init_params {
114 /* Minimum idle filter value in Us */
115 u32 min_idle_filter_us;
116
117 /*
118 * Minimum Targeted Saving in Us. AP will update idle thresholds only
119 * if power saving achieved by updating idle thresholds is greater than
120 * Minimum targeted saving.
121 */
122 u32 min_target_saving_us;
123
124 /* Minimum targeted residency of power feature in Us */
125 u32 power_break_even_us;
126
127 /*
128 * Maximum number of allowed power feature cycles per sample.
129 *
130 * We are allowing at max "pgPerSampleMax" cycles in one iteration of AP
131 * AKA pgPerSampleMax in original algorithm.
132 */
133 u32 cycles_per_sample_max;
134};
135
136/* AP Commands/Message structures */
137
138/*
139 * Structure for Generic AP Commands
140 */
141struct pmu_ap_cmd_common {
142 u8 cmd_type;
143 u16 cmd_id;
144};
145
146/*
147 * Structure for INIT AP command
148 */
149struct pmu_ap_cmd_init {
150 u8 cmd_type;
151 u16 cmd_id;
152 u8 rsvd;
153 u32 pg_sampling_period_us;
154};
155
156/*
157 * Structure for Enable/Disable ApCtrl Commands
158 */
159struct pmu_ap_cmd_enable_ctrl {
160 u8 cmd_type;
161 u16 cmd_id;
162
163 u8 ctrl_id;
164};
165
166struct pmu_ap_cmd_disable_ctrl {
167 u8 cmd_type;
168 u16 cmd_id;
169
170 u8 ctrl_id;
171};
172
173/*
174 * Structure for INIT command
175 */
176struct pmu_ap_cmd_init_ctrl {
177 u8 cmd_type;
178 u16 cmd_id;
179 u8 ctrl_id;
180 struct pmu_ap_ctrl_init_params params;
181};
182
183struct pmu_ap_cmd_init_and_enable_ctrl {
184 u8 cmd_type;
185 u16 cmd_id;
186 u8 ctrl_id;
187 struct pmu_ap_ctrl_init_params params;
188};
189
190/*
191 * Structure for KICK_CTRL command
192 */
193struct pmu_ap_cmd_kick_ctrl {
194 u8 cmd_type;
195 u16 cmd_id;
196 u8 ctrl_id;
197
198 u32 skip_count;
199};
200
201/*
202 * Structure for PARAM command
203 */
204struct pmu_ap_cmd_param {
205 u8 cmd_type;
206 u16 cmd_id;
207 u8 ctrl_id;
208
209 u32 data;
210};
211
212/*
213 * Defines for AP commands
214 */
215enum {
216 PMU_AP_CMD_ID_INIT = 0x0 ,
217 PMU_AP_CMD_ID_INIT_AND_ENABLE_CTRL,
218 PMU_AP_CMD_ID_ENABLE_CTRL ,
219 PMU_AP_CMD_ID_DISABLE_CTRL ,
220 PMU_AP_CMD_ID_KICK_CTRL ,
221};
222
223/*
224 * AP Command
225 */
226union pmu_ap_cmd {
227 u8 cmd_type;
228 struct pmu_ap_cmd_common cmn;
229 struct pmu_ap_cmd_init init;
230 struct pmu_ap_cmd_init_and_enable_ctrl init_and_enable_ctrl;
231 struct pmu_ap_cmd_enable_ctrl enable_ctrl;
232 struct pmu_ap_cmd_disable_ctrl disable_ctrl;
233 struct pmu_ap_cmd_kick_ctrl kick_ctrl;
234};
235
236/*
237 * Structure for generic AP Message
238 */
239struct pmu_ap_msg_common {
240 u8 msg_type;
241 u16 msg_id;
242};
243
244/*
245 * Structure for INIT_ACK Message
246 */
247struct pmu_ap_msg_init_ack {
248 u8 msg_type;
249 u16 msg_id;
250 u8 ctrl_id;
251 u32 stats_dmem_offset;
252};
253
254/*
255 * Defines for AP messages
256 */
257enum {
258 PMU_AP_MSG_ID_INIT_ACK = 0x0,
259};
260
261/*
262 * AP Message
263 */
264union pmu_ap_msg {
265 u8 msg_type;
266 struct pmu_ap_msg_common cmn;
267 struct pmu_ap_msg_init_ack init_ack;
268};
269
270/* Default Sampling Period of AELPG */
271#define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US (1000000)
272
273/* Default values of APCTRL parameters */
274#define APCTRL_MINIMUM_IDLE_FILTER_DEFAULT_US (100)
275#define APCTRL_MINIMUM_TARGET_SAVING_DEFAULT_US (10000)
276#define APCTRL_POWER_BREAKEVEN_DEFAULT_US (2000)
277#define APCTRL_CYCLES_PER_SAMPLE_MAX_DEFAULT (200)
278
279/*
280 * Disable reason for Adaptive Power Controller
281 */
282enum {
283 APCTRL_DISABLE_REASON_RM_UNLOAD,
284 APCTRL_DISABLE_REASON_RMCTRL,
285};
286
287/*
288 * Adaptive Power Controller
289 */
290struct ap_ctrl {
291 u32 stats_dmem_offset;
292 u32 disable_reason_mask;
293 struct pmu_ap_ctrl_stat stat_cache;
294 u8 b_ready;
295};
296
297/*
298 * Adaptive Power structure
299 *
300 * ap structure provides generic infrastructure to make any power feature
301 * adaptive.
302 */
303struct pmu_ap {
304 u32 supported_mask;
305 struct ap_ctrl ap_ctrl[PMU_AP_CTRL_ID_MAX];
306};
307
308enum { 56enum {
309 GK20A_PMU_DMAIDX_UCODE = 0, 57 GK20A_PMU_DMAIDX_UCODE = 0,
310 GK20A_PMU_DMAIDX_VIRT = 1, 58 GK20A_PMU_DMAIDX_VIRT = 1,
@@ -316,88 +64,6 @@ enum {
316 GK20A_PMU_DMAIDX_END = 7 64 GK20A_PMU_DMAIDX_END = 7
317}; 65};
318 66
319struct falc_u64 {
320 u32 lo;
321 u32 hi;
322};
323
324struct falc_dma_addr {
325 u32 dma_base;
326 /*dma_base1 is 9-bit MSB for FB Base
327 *address for the transfer in FB after
328 *address using 49b FB address*/
329 u16 dma_base1;
330 u8 dma_offset;
331};
332
333struct pmu_mem_v0 {
334 u32 dma_base;
335 u8 dma_offset;
336 u8 dma_idx;
337};
338
339struct pmu_mem_v1 {
340 u32 dma_base;
341 u8 dma_offset;
342 u8 dma_idx;
343 u16 fb_size;
344};
345
346struct pmu_mem_v2 {
347 struct falc_dma_addr dma_addr;
348 u8 dma_idx;
349 u16 fb_size;
350};
351
352struct pmu_mem_desc_v0 {
353 /*!
354 * Start address of memory surface that is being communicated to the falcon.
355 */
356 struct falc_u64 dma_addr;
357 /*!
358 * Max allowed DMA transfer size (size of the memory surface). Accesses past
359 * this point may result in page faults and/or memory corruptions.
360 */
361 u16 dma_sizemax;
362 /*!
363 * DMA channel index to be used when accessing this surface.
364 */
365 u8 dma_idx;
366};
367
368struct pmu_dmem {
369 u16 size;
370 u32 offset;
371};
372
373/* Make sure size of this structure is a multiple of 4 bytes */
374struct pmu_cmdline_args_v0 {
375 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
376 u32 falc_trace_size; /* falctrace buffer size (bytes) */
377 u32 falc_trace_dma_base; /* 256-byte block address */
378 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
379 struct pmu_mem_v0 gc6_ctx; /* dmem offset of gc6 context */
380};
381
382struct pmu_cmdline_args_v1 {
383 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
384 u32 falc_trace_size; /* falctrace buffer size (bytes) */
385 u32 falc_trace_dma_base; /* 256-byte block address */
386 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
387 u8 secure_mode;
388 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */
389};
390
391struct flcn_u64 {
392 u32 lo;
393 u32 hi;
394};
395
396struct flcn_mem_desc_v0 {
397 struct flcn_u64 address;
398 u32 params;
399};
400
401struct pmu_cmdline_args_v2 { 67struct pmu_cmdline_args_v2 {
402 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */ 68 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
403 u32 falc_trace_size; /* falctrace buffer size (bytes) */ 69 u32 falc_trace_size; /* falctrace buffer size (bytes) */
@@ -528,47 +194,11 @@ struct pmu_ucode_desc_v1 {
528#define PMU_CMD_FLAGS_EVENT BIT(2) 194#define PMU_CMD_FLAGS_EVENT BIT(2)
529#define PMU_CMD_FLAGS_WATERMARK BIT(3) 195#define PMU_CMD_FLAGS_WATERMARK BIT(3)
530 196
531struct pmu_hdr {
532 u8 unit_id;
533 u8 size;
534 u8 ctrl_flags;
535 u8 seq_id;
536};
537#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr) 197#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr)
538#define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr) 198#define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr)
539 199
540#define PMU_QUEUE_COUNT 5 200#define PMU_QUEUE_COUNT 5
541 201
542struct pmu_allocation_v0 {
543 u8 pad[3];
544 u8 fb_mem_use;
545 struct {
546 struct pmu_dmem dmem;
547 struct pmu_mem_v0 fb;
548 } alloc;
549};
550
551struct pmu_allocation_v1 {
552 struct {
553 struct pmu_dmem dmem;
554 struct pmu_mem_v1 fb;
555 } alloc;
556};
557
558struct pmu_allocation_v2 {
559 struct {
560 struct pmu_dmem dmem;
561 struct pmu_mem_desc_v0 fb;
562 } alloc;
563};
564
565struct pmu_allocation_v3 {
566 struct {
567 struct pmu_dmem dmem;
568 struct flcn_mem_desc_v0 fb;
569 } alloc;
570};
571
572enum { 202enum {
573 PMU_INIT_MSG_TYPE_PMU_INIT = 0, 203 PMU_INIT_MSG_TYPE_PMU_INIT = 0,
574}; 204};
@@ -652,56 +282,6 @@ struct pmu_init_msg {
652}; 282};
653 283
654enum { 284enum {
655 PMU_PG_ELPG_MSG_INIT_ACK,
656 PMU_PG_ELPG_MSG_DISALLOW_ACK,
657 PMU_PG_ELPG_MSG_ALLOW_ACK,
658 PMU_PG_ELPG_MSG_FREEZE_ACK,
659 PMU_PG_ELPG_MSG_FREEZE_ABORT,
660 PMU_PG_ELPG_MSG_UNFREEZE_ACK,
661};
662
663struct pmu_pg_msg_elpg_msg {
664 u8 msg_type;
665 u8 engine_id;
666 u16 msg;
667};
668
669enum {
670 PMU_PG_STAT_MSG_RESP_DMEM_OFFSET = 0,
671};
672
673struct pmu_pg_msg_stat {
674 u8 msg_type;
675 u8 engine_id;
676 u16 sub_msg_id;
677 u32 data;
678};
679
680enum {
681 PMU_PG_MSG_ENG_BUF_LOADED,
682 PMU_PG_MSG_ENG_BUF_UNLOADED,
683 PMU_PG_MSG_ENG_BUF_FAILED,
684};
685
686struct pmu_pg_msg_eng_buf_stat {
687 u8 msg_type;
688 u8 engine_id;
689 u8 buf_idx;
690 u8 status;
691};
692
693struct pmu_pg_msg {
694 union {
695 u8 msg_type;
696 struct pmu_pg_msg_elpg_msg elpg_msg;
697 struct pmu_pg_msg_stat stat;
698 struct pmu_pg_msg_eng_buf_stat eng_buf_stat;
699 /* TBD: other pg messages */
700 union pmu_ap_msg ap_msg;
701 };
702};
703
704enum {
705 PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0, 285 PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
706}; 286};
707 287
@@ -738,175 +318,6 @@ enum {
738 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE 318 PMU_PG_CMD_ID_PWR_RAIL_SMU_MSG_DISABLE
739}; 319};
740 320
741enum {
742 PMU_PG_ELPG_CMD_INIT,
743 PMU_PG_ELPG_CMD_DISALLOW,
744 PMU_PG_ELPG_CMD_ALLOW,
745 PMU_PG_ELPG_CMD_FREEZE,
746 PMU_PG_ELPG_CMD_UNFREEZE,
747};
748
749struct pmu_pg_cmd_elpg_cmd {
750 u8 cmd_type;
751 u8 engine_id;
752 u16 cmd;
753};
754
755struct pmu_pg_cmd_eng_buf_load_v0 {
756 u8 cmd_type;
757 u8 engine_id;
758 u8 buf_idx;
759 u8 pad;
760 u16 buf_size;
761 u32 dma_base;
762 u8 dma_offset;
763 u8 dma_idx;
764};
765
766struct pmu_pg_cmd_eng_buf_load_v1 {
767 u8 cmd_type;
768 u8 engine_id;
769 u8 buf_idx;
770 u8 pad;
771 struct flcn_mem_desc {
772 struct falc_u64 dma_addr;
773 u16 dma_size;
774 u8 dma_idx;
775 } dma_desc;
776};
777
778struct pmu_pg_cmd_eng_buf_load_v2 {
779 u8 cmd_type;
780 u8 engine_id;
781 u8 buf_idx;
782 u8 pad;
783 struct flcn_mem_desc_v0 dma_desc;
784};
785
786enum {
787 PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
788};
789
790#define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0
791
792#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
793#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED (1 << 2)
794
795struct pmu_pg_cmd_gr_init_param {
796 u8 cmd_type;
797 u16 sub_cmd_id;
798 u8 featuremask;
799};
800
801struct pmu_pg_cmd_stat {
802 u8 cmd_type;
803 u8 engine_id;
804 u16 sub_cmd_id;
805 u32 data;
806};
807
808struct pmu_pg_cmd {
809 union {
810 u8 cmd_type;
811 struct pmu_pg_cmd_elpg_cmd elpg_cmd;
812 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
813 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
814 struct pmu_pg_cmd_eng_buf_load_v2 eng_buf_load_v2;
815 struct pmu_pg_cmd_stat stat;
816 struct pmu_pg_cmd_gr_init_param gr_init_param;
817 /* TBD: other pg commands */
818 union pmu_ap_cmd ap_cmd;
819 };
820};
821
822/* ACR Commands/Message structures */
823
824enum {
825 PMU_ACR_CMD_ID_INIT_WPR_REGION = 0x0 ,
826 PMU_ACR_CMD_ID_BOOTSTRAP_FALCON,
827 PMU_ACR_CMD_ID_RESERVED,
828 PMU_ACR_CMD_ID_BOOTSTRAP_MULTIPLE_FALCONS,
829};
830
831/*
832 * Initializes the WPR region details
833 */
834struct pmu_acr_cmd_init_wpr_details {
835 u8 cmd_type;
836 u32 regionid;
837 u32 wproffset;
838
839};
840
841/*
842 * falcon ID to bootstrap
843 */
844struct pmu_acr_cmd_bootstrap_falcon {
845 u8 cmd_type;
846 u32 flags;
847 u32 falconid;
848};
849
850/*
851 * falcon ID to bootstrap
852 */
853struct pmu_acr_cmd_bootstrap_multiple_falcons {
854 u8 cmd_type;
855 u32 flags;
856 u32 falconidmask;
857 u32 usevamask;
858 struct falc_u64 wprvirtualbase;
859};
860
861#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_NO 1
862#define PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0
863
864
865struct pmu_acr_cmd {
866 union {
867 u8 cmd_type;
868 struct pmu_acr_cmd_bootstrap_falcon bootstrap_falcon;
869 struct pmu_acr_cmd_init_wpr_details init_wpr;
870 struct pmu_acr_cmd_bootstrap_multiple_falcons boot_falcons;
871 };
872};
873
874/* acr messages */
875
876/*
877 * returns the WPR region init information
878 */
879#define PMU_ACR_MSG_ID_INIT_WPR_REGION 0
880
881/*
882 * Returns the Bootstrapped falcon ID to RM
883 */
884#define PMU_ACR_MSG_ID_BOOTSTRAP_FALCON 1
885
886/*
887 * Returns the WPR init status
888 */
889#define PMU_ACR_SUCCESS 0
890#define PMU_ACR_ERROR 1
891
892/*
893 * PMU notifies about bootstrap status of falcon
894 */
895struct pmu_acr_msg_bootstrap_falcon {
896 u8 msg_type;
897 union {
898 u32 errorcode;
899 u32 falconid;
900 };
901};
902
903struct pmu_acr_msg {
904 union {
905 u8 msg_type;
906 struct pmu_acr_msg_bootstrap_falcon acrmsg;
907 };
908};
909
910/***************************** ACR ERROR CODES ******************************/ 321/***************************** ACR ERROR CODES ******************************/
911/*! 322/*!
912 * Error codes used in PMU-ACR Task 323 * Error codes used in PMU-ACR Task
@@ -922,47 +333,6 @@ struct pmu_acr_msg {
922#define PMU_DOMAIN_GROUP_GPC2CLK 1 333#define PMU_DOMAIN_GROUP_GPC2CLK 1
923#define PMU_DOMAIN_GROUP_NUM 2 334#define PMU_DOMAIN_GROUP_NUM 2
924 335
925/* FECS mem override command*/
926
927#define PMU_LRF_TEX_LTC_DRAM_CMD_ID_EN_DIS 0
928
929/*!
930 * Enable/Disable FECS error feature
931 */
932struct pmu_cmd_lrf_tex_ltc_dram_en_dis {
933 /*Command type must be first*/
934 u8 cmd_type;
935 /*unit bitmask*/
936 u8 en_dis_mask;
937};
938
939struct pmu_lrf_tex_ltc_dram_cmd {
940 union {
941 u8 cmd_type;
942 struct pmu_cmd_lrf_tex_ltc_dram_en_dis en_dis;
943 };
944};
945
946/* FECS mem override messages*/
947#define PMU_LRF_TEX_LTC_DRAM_MSG_ID_EN_DIS 0
948
949struct pmu_msg_lrf_tex_ltc_dram_en_dis {
950 /*!
951 * Must be at start
952 */
953 u8 msg_type;
954 u8 en_fail_mask;
955 u8 dis_fail_mask;
956 u32 pmu_status;
957};
958
959struct pmu_lrf_tex_ltc_dram_msg {
960 union {
961 u8 msg_type;
962 struct pmu_msg_lrf_tex_ltc_dram_en_dis en_dis;
963 };
964};
965
966/* TBD: smart strategy */ 336/* TBD: smart strategy */
967#define PMU_PERFMON_PCT_TO_INC 58 337#define PMU_PERFMON_PCT_TO_INC 58
968#define PMU_PERFMON_PCT_TO_DEC 23 338#define PMU_PERFMON_PCT_TO_DEC 23
@@ -990,136 +360,6 @@ struct pmu_perfmon_counter_v2 {
990#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002) 360#define PMU_PERFMON_FLAG_ENABLE_DECREASE (0x00000002)
991#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) 361#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004)
992 362
993/* PERFMON CMD */
994enum {
995 PMU_PERFMON_CMD_ID_START = 0,
996 PMU_PERFMON_CMD_ID_STOP = 1,
997 PMU_PERFMON_CMD_ID_INIT = 2
998};
999
1000struct pmu_perfmon_cmd_start_v3 {
1001 u8 cmd_type;
1002 u8 group_id;
1003 u8 state_id;
1004 u8 flags;
1005 struct pmu_allocation_v3 counter_alloc;
1006};
1007
1008struct pmu_perfmon_cmd_start_v2 {
1009 u8 cmd_type;
1010 u8 group_id;
1011 u8 state_id;
1012 u8 flags;
1013 struct pmu_allocation_v2 counter_alloc;
1014};
1015
1016struct pmu_perfmon_cmd_start_v1 {
1017 u8 cmd_type;
1018 u8 group_id;
1019 u8 state_id;
1020 u8 flags;
1021 struct pmu_allocation_v1 counter_alloc;
1022};
1023
1024struct pmu_perfmon_cmd_start_v0 {
1025 u8 cmd_type;
1026 u8 group_id;
1027 u8 state_id;
1028 u8 flags;
1029 struct pmu_allocation_v0 counter_alloc;
1030};
1031
1032struct pmu_perfmon_cmd_stop {
1033 u8 cmd_type;
1034};
1035
1036struct pmu_perfmon_cmd_init_v3 {
1037 u8 cmd_type;
1038 u8 to_decrease_count;
1039 u8 base_counter_id;
1040 u32 sample_period_us;
1041 struct pmu_allocation_v3 counter_alloc;
1042 u8 num_counters;
1043 u8 samples_in_moving_avg;
1044 u16 sample_buffer;
1045};
1046
1047struct pmu_perfmon_cmd_init_v2 {
1048 u8 cmd_type;
1049 u8 to_decrease_count;
1050 u8 base_counter_id;
1051 u32 sample_period_us;
1052 struct pmu_allocation_v2 counter_alloc;
1053 u8 num_counters;
1054 u8 samples_in_moving_avg;
1055 u16 sample_buffer;
1056};
1057
1058struct pmu_perfmon_cmd_init_v1 {
1059 u8 cmd_type;
1060 u8 to_decrease_count;
1061 u8 base_counter_id;
1062 u32 sample_period_us;
1063 struct pmu_allocation_v1 counter_alloc;
1064 u8 num_counters;
1065 u8 samples_in_moving_avg;
1066 u16 sample_buffer;
1067};
1068
1069struct pmu_perfmon_cmd_init_v0 {
1070 u8 cmd_type;
1071 u8 to_decrease_count;
1072 u8 base_counter_id;
1073 u32 sample_period_us;
1074 struct pmu_allocation_v0 counter_alloc;
1075 u8 num_counters;
1076 u8 samples_in_moving_avg;
1077 u16 sample_buffer;
1078};
1079
1080struct pmu_perfmon_cmd {
1081 union {
1082 u8 cmd_type;
1083 struct pmu_perfmon_cmd_start_v0 start_v0;
1084 struct pmu_perfmon_cmd_start_v1 start_v1;
1085 struct pmu_perfmon_cmd_start_v2 start_v2;
1086 struct pmu_perfmon_cmd_start_v3 start_v3;
1087 struct pmu_perfmon_cmd_stop stop;
1088 struct pmu_perfmon_cmd_init_v0 init_v0;
1089 struct pmu_perfmon_cmd_init_v1 init_v1;
1090 struct pmu_perfmon_cmd_init_v2 init_v2;
1091 struct pmu_perfmon_cmd_init_v3 init_v3;
1092 };
1093};
1094
1095struct pmu_zbc_cmd {
1096 u8 cmd_type;
1097 u8 pad;
1098 u16 entry_mask;
1099};
1100
1101/* PERFMON MSG */
1102enum {
1103 PMU_PERFMON_MSG_ID_INCREASE_EVENT = 0,
1104 PMU_PERFMON_MSG_ID_DECREASE_EVENT = 1,
1105 PMU_PERFMON_MSG_ID_INIT_EVENT = 2,
1106 PMU_PERFMON_MSG_ID_ACK = 3
1107};
1108
1109struct pmu_perfmon_msg_generic {
1110 u8 msg_type;
1111 u8 state_id;
1112 u8 group_id;
1113 u8 data;
1114};
1115
1116struct pmu_perfmon_msg {
1117 union {
1118 u8 msg_type;
1119 struct pmu_perfmon_msg_generic gen;
1120 };
1121};
1122
1123 363
1124struct pmu_cmd { 364struct pmu_cmd {
1125 struct pmu_hdr hdr; 365 struct pmu_hdr hdr;
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 17:25:01 -0400