gpu: nvgpu: per-chip GPCCS exception support

Adding support for ISR handling of GPCCS exceptions

JIRA: GPUT19X-83

Change-Id: Ia5550aac8f368d8915f6c94aa22478cacbb2bddc
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1480992
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 13 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index b3292ac4..3d1e0847 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -309,6 +309,8 @@ struct gpu_ops {
                                 u32 *hww_global_esr);
                 int (*handle_tex_exception)(struct gk20a *g, u32 gpc, u32 tpc,
                                                 bool *post_event);
+                int (*handle_gpc_gpccs_exception)(struct gk20a *g, u32 gpc,
+                                                u32 gpc_exception);
                 void (*enable_gpc_exceptions)(struct gk20a *g);
                 void (*create_gr_sysfs)(struct device *dev);
                 u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g);
@@ -749,6 +751,8 @@ struct gpu_ops {
                 u32  lspmuwprinitdone;
                 u32  lsfloadedfalconid;
                 bool fecsbootstrapdone;
+                void (*handle_ext_irq)(struct gk20a *g, u32 intr);
+                void (*set_irqmask)(struct gk20a *g);
         } pmu;
         struct {
                 void (*disable_slowboot)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 9bd07894..1891d98f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6350,13 +6350,21 @@ static int gk20a_gr_handle_gpc_exception(struct gk20a *g, bool *post_event,
                 }
 
                 /* Handle GCC exception */
-                if(gr_gpc0_gpccs_gpc_exception_gcc_v(gpc_exception) &&
+                if (gr_gpc0_gpccs_gpc_exception_gcc_v(gpc_exception) &&
                                 g->ops.gr.handle_gcc_exception) {
                         int gcc_ret = 0;
                         gcc_ret = g->ops.gr.handle_gcc_exception(g, gpc, tpc,
                                 post_event, fault_ch, hww_global_esr);
                         ret = ret ? ret : gcc_ret;
                 }
+
+                /* Handle GPCCS exceptions */
+                if (g->ops.gr.handle_gpc_gpccs_exception) {
+                        int ret_ecc = 0;
+                        ret_ecc = g->ops.gr.handle_gpc_gpccs_exception(g, gpc,
+                                                                gpc_exception);
+                        ret = ret ? ret : ret_ecc;
+                }
         }
 
         return ret;