diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2016-08-22 16:20:05 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-09-12 13:46:37 -0400 |
commit | 51b5ec852096c0eeb1eaca48ae132d7bf9ac7a9d (patch) | |
tree | 0c182e08ae521ccc449ebdd6abdc0180ed3c98df /drivers | |
parent | 2c6652f182d84dc7ec4218576b65ad582f05d4a6 (diff) |
gpu: nvgpu: gv11b: hw header update
Updated hw headers to CL#37001916. Some of
important changes include new door bell user
mode mechanism and new runlist structure.
Bug 1735765
Change-Id: Icf01156dd3e7d94466f553ffc53267e4043e1188
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1205888
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 63 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 830 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 42 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 128 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | 356 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h | 89 |
15 files changed, 465 insertions, 1157 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 9d0b4ade..088ec040 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -72,16 +72,16 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
72 | gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); | 72 | gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); |
73 | 73 | ||
74 | /* Check for LRF ECC errors. */ | 74 | /* Check for LRF ECC errors. */ |
75 | lrf_ecc_status = gk20a_readl(g, | 75 | lrf_ecc_status = gk20a_readl(g, |
76 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); | 76 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); |
77 | if ( (lrf_ecc_status & | 77 | if ((lrf_ecc_status & |
78 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || | 78 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || |
79 | (lrf_ecc_status & | 79 | (lrf_ecc_status & |
80 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || | 80 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || |
81 | (lrf_ecc_status & | 81 | (lrf_ecc_status & |
82 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || | 82 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || |
83 | (lrf_ecc_status & | 83 | (lrf_ecc_status & |
84 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f()) ) { | 84 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f())) { |
85 | 85 | ||
86 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | 86 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, |
87 | "Single bit error detected in SM LRF!"); | 87 | "Single bit error detected in SM LRF!"); |
@@ -93,14 +93,14 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
93 | gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, | 93 | gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, |
94 | 0); | 94 | 0); |
95 | } | 95 | } |
96 | if ( (lrf_ecc_status & | 96 | if ((lrf_ecc_status & |
97 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || | 97 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || |
98 | (lrf_ecc_status & | 98 | (lrf_ecc_status & |
99 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || | 99 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || |
100 | (lrf_ecc_status & | 100 | (lrf_ecc_status & |
101 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || | 101 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || |
102 | (lrf_ecc_status & | 102 | (lrf_ecc_status & |
103 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f()) ) { | 103 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f())) { |
104 | 104 | ||
105 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | 105 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, |
106 | "Double bit error detected in SM LRF!"); | 106 | "Double bit error detected in SM LRF!"); |
@@ -109,14 +109,13 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
109 | gk20a_readl(g, | 109 | gk20a_readl(g, |
110 | gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); | 110 | gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); |
111 | gk20a_writel(g, | 111 | gk20a_writel(g, |
112 | gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, | 112 | gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, 0); |
113 | 0); | ||
114 | } | 113 | } |
115 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | 114 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, |
116 | lrf_ecc_status); | 115 | lrf_ecc_status); |
117 | 116 | ||
118 | /* Check for SHM ECC errors. */ | 117 | /* Check for SHM ECC errors. */ |
119 | shm_ecc_status = gk20a_readl(g, | 118 | shm_ecc_status = gk20a_readl(g, |
120 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); | 119 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); |
121 | if ((shm_ecc_status & | 120 | if ((shm_ecc_status & |
122 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || | 121 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || |
@@ -125,7 +124,7 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
125 | (shm_ecc_status & | 124 | (shm_ecc_status & |
126 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || | 125 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || |
127 | (shm_ecc_status & | 126 | (shm_ecc_status & |
128 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f()) ) { | 127 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f())) { |
129 | u32 ecc_stats_reg_val; | 128 | u32 ecc_stats_reg_val; |
130 | 129 | ||
131 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | 130 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, |
@@ -144,10 +143,10 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
144 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, | 143 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, |
145 | ecc_stats_reg_val); | 144 | ecc_stats_reg_val); |
146 | } | 145 | } |
147 | if ( (shm_ecc_status & | 146 | if ((shm_ecc_status & |
148 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || | 147 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || |
149 | (shm_ecc_status & | 148 | (shm_ecc_status & |
150 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f()) ) { | 149 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f())) { |
151 | u32 ecc_stats_reg_val; | 150 | u32 ecc_stats_reg_val; |
152 | 151 | ||
153 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | 152 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, |
@@ -1133,8 +1132,8 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | |||
1133 | gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r())); | 1132 | gk20a_readl(g, gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r())); |
1134 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", | 1133 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_FS: 0x%x\n", |
1135 | gk20a_readl(g, gr_cwd_fs_r())); | 1134 | gk20a_readl(g, gr_cwd_fs_r())); |
1136 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS: 0x%x\n", | 1135 | gk20a_debug_output(o, "NV_PGRAPH_PRI_FE_TPC_FS(0): 0x%x\n", |
1137 | gk20a_readl(g, gr_fe_tpc_fs_r())); | 1136 | gk20a_readl(g, gr_fe_tpc_fs_r(0))); |
1138 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n", | 1137 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_GPC_TPC_ID: 0x%x\n", |
1139 | gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); | 1138 | gk20a_readl(g, gr_cwd_gpc_tpc_id_r(0))); |
1140 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", | 1139 | gk20a_debug_output(o, "NV_PGRAPH_PRI_CWD_SM_ID(0): 0x%x\n", |
@@ -1184,7 +1183,7 @@ static int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | |||
1184 | 1183 | ||
1185 | static bool gr_activity_empty_or_preempted(u32 val) | 1184 | static bool gr_activity_empty_or_preempted(u32 val) |
1186 | { | 1185 | { |
1187 | while(val) { | 1186 | while (val) { |
1188 | u32 v = val & 7; | 1187 | u32 v = val & 7; |
1189 | if (v != gr_activity_4_gpc0_empty_v() && | 1188 | if (v != gr_activity_4_gpc0_empty_v() && |
1190 | v != gr_activity_4_gpc0_preempted_v()) | 1189 | v != gr_activity_4_gpc0_preempted_v()) |
@@ -1542,16 +1541,16 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1542 | gpc, tpc, global_esr); | 1541 | gpc, tpc, global_esr); |
1543 | 1542 | ||
1544 | if (cilp_enabled && sm_debugger_attached) { | 1543 | if (cilp_enabled && sm_debugger_attached) { |
1545 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) | 1544 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) |
1546 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 1545 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, |
1547 | gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()); | 1546 | gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()); |
1548 | 1547 | ||
1549 | if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()) | 1548 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()) |
1550 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | 1549 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, |
1551 | gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f()); | 1550 | gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()); |
1552 | 1551 | ||
1553 | global_mask = gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f() | | 1552 | global_mask = gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f() | |
1554 | gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(); | 1553 | gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(); |
1555 | 1554 | ||
1556 | if (warp_esr != 0 || (global_esr & global_mask) != 0) { | 1555 | if (warp_esr != 0 || (global_esr & global_mask) != 0) { |
1557 | *ignore_debugger = true; | 1556 | *ignore_debugger = true; |
@@ -1575,7 +1574,7 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1575 | } | 1574 | } |
1576 | 1575 | ||
1577 | /* reset the HWW errors after locking down */ | 1576 | /* reset the HWW errors after locking down */ |
1578 | global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | 1577 | global_esr_copy = gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset); |
1579 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); | 1578 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); |
1580 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1579 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1581 | "CILP: HWWs cleared for gpc %d tpc %d\n", | 1580 | "CILP: HWWs cleared for gpc %d tpc %d\n", |
@@ -1588,15 +1587,15 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1588 | return ret; | 1587 | return ret; |
1589 | } | 1588 | } |
1590 | 1589 | ||
1591 | dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); | 1590 | dbgr_control0 = gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset); |
1592 | if (dbgr_control0 & gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f()) { | 1591 | if (dbgr_control0 & gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f()) { |
1593 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1592 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1594 | "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", | 1593 | "CILP: clearing SINGLE_STEP_MODE before resume for gpc %d tpc %d\n", |
1595 | gpc, tpc); | 1594 | gpc, tpc); |
1596 | dbgr_control0 = set_field(dbgr_control0, | 1595 | dbgr_control0 = set_field(dbgr_control0, |
1597 | gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(), | 1596 | gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(), |
1598 | gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f()); | 1597 | gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f()); |
1599 | gk20a_writel(g, gr_gpc0_tpc0_sm_dbgr_control0_r() + offset, dbgr_control0); | 1598 | gk20a_writel(g, gr_gpc0_tpc0_sm0_dbgr_control0_r() + offset, dbgr_control0); |
1600 | } | 1599 | } |
1601 | 1600 | ||
1602 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1601 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
@@ -1703,10 +1702,10 @@ clean_up: | |||
1703 | 1702 | ||
1704 | static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) | 1703 | static u32 gv11b_mask_hww_warp_esr(u32 hww_warp_esr) |
1705 | { | 1704 | { |
1706 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) | 1705 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m())) |
1707 | hww_warp_esr = set_field(hww_warp_esr, | 1706 | hww_warp_esr = set_field(hww_warp_esr, |
1708 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), | 1707 | gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(), |
1709 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f()); | 1708 | gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f()); |
1710 | 1709 | ||
1711 | return hww_warp_esr; | 1710 | return hww_warp_esr; |
1712 | } | 1711 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h index c06a106a..66571ae7 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_bus_gv11b.h | |||
@@ -50,6 +50,30 @@ | |||
50 | #ifndef _hw_bus_gv11b_h_ | 50 | #ifndef _hw_bus_gv11b_h_ |
51 | #define _hw_bus_gv11b_h_ | 51 | #define _hw_bus_gv11b_h_ |
52 | 52 | ||
53 | static inline u32 bus_bar0_window_r(void) | ||
54 | { | ||
55 | return 0x00001700; | ||
56 | } | ||
57 | static inline u32 bus_bar0_window_base_f(u32 v) | ||
58 | { | ||
59 | return (v & 0xffffff) << 0; | ||
60 | } | ||
61 | static inline u32 bus_bar0_window_target_vid_mem_f(void) | ||
62 | { | ||
63 | return 0x0; | ||
64 | } | ||
65 | static inline u32 bus_bar0_window_target_sys_mem_coherent_f(void) | ||
66 | { | ||
67 | return 0x2000000; | ||
68 | } | ||
69 | static inline u32 bus_bar0_window_target_sys_mem_noncoherent_f(void) | ||
70 | { | ||
71 | return 0x3000000; | ||
72 | } | ||
73 | static inline u32 bus_bar0_window_target_bar0_window_base_shift_v(void) | ||
74 | { | ||
75 | return 0x00000010; | ||
76 | } | ||
53 | static inline u32 bus_bar1_block_r(void) | 77 | static inline u32 bus_bar1_block_r(void) |
54 | { | 78 | { |
55 | return 0x00001704; | 79 | return 0x00001704; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h index 900054aa..9e4bab8b 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fb_gv11b.h | |||
@@ -174,18 +174,6 @@ static inline u32 fb_mmu_invalidate_replay_start_ack_all_f(void) | |||
174 | { | 174 | { |
175 | return 0x10; | 175 | return 0x10; |
176 | } | 176 | } |
177 | static inline u32 fb_mmu_invalidate_replay_cancel_targeted_f(void) | ||
178 | { | ||
179 | return 0x18; | ||
180 | } | ||
181 | static inline u32 fb_mmu_invalidate_replay_cancel_global_f(void) | ||
182 | { | ||
183 | return 0x20; | ||
184 | } | ||
185 | static inline u32 fb_mmu_invalidate_replay_cancel_f(void) | ||
186 | { | ||
187 | return 0x20; | ||
188 | } | ||
189 | static inline u32 fb_mmu_invalidate_sys_membar_s(void) | 177 | static inline u32 fb_mmu_invalidate_sys_membar_s(void) |
190 | { | 178 | { |
191 | return 1; | 179 | return 1; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 9c0f2483..8af66362 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | |||
@@ -104,7 +104,7 @@ static inline u32 fifo_eng_runlist_base_r(u32 i) | |||
104 | } | 104 | } |
105 | static inline u32 fifo_eng_runlist_base__size_1_v(void) | 105 | static inline u32 fifo_eng_runlist_base__size_1_v(void) |
106 | { | 106 | { |
107 | return 0x00000001; | 107 | return 0x00000002; |
108 | } | 108 | } |
109 | static inline u32 fifo_eng_runlist_r(u32 i) | 109 | static inline u32 fifo_eng_runlist_r(u32 i) |
110 | { | 110 | { |
@@ -112,7 +112,7 @@ static inline u32 fifo_eng_runlist_r(u32 i) | |||
112 | } | 112 | } |
113 | static inline u32 fifo_eng_runlist__size_1_v(void) | 113 | static inline u32 fifo_eng_runlist__size_1_v(void) |
114 | { | 114 | { |
115 | return 0x00000001; | 115 | return 0x00000002; |
116 | } | 116 | } |
117 | static inline u32 fifo_eng_runlist_length_f(u32 v) | 117 | static inline u32 fifo_eng_runlist_length_f(u32 v) |
118 | { | 118 | { |
@@ -268,7 +268,7 @@ static inline u32 fifo_intr_mmu_fault_id_r(void) | |||
268 | } | 268 | } |
269 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) | 269 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) |
270 | { | 270 | { |
271 | return 0x00000000; | 271 | return 0x00000040; |
272 | } | 272 | } |
273 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) | 273 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) |
274 | { | 274 | { |
@@ -332,7 +332,7 @@ static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) | |||
332 | } | 332 | } |
333 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) | 333 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) |
334 | { | 334 | { |
335 | return 0x00000001; | 335 | return 0x00000003; |
336 | } | 336 | } |
337 | static inline u32 fifo_intr_runlist_r(void) | 337 | static inline u32 fifo_intr_runlist_r(void) |
338 | { | 338 | { |
@@ -412,7 +412,7 @@ static inline u32 fifo_engine_status_r(u32 i) | |||
412 | } | 412 | } |
413 | static inline u32 fifo_engine_status__size_1_v(void) | 413 | static inline u32 fifo_engine_status__size_1_v(void) |
414 | { | 414 | { |
415 | return 0x00000002; | 415 | return 0x00000004; |
416 | } | 416 | } |
417 | static inline u32 fifo_engine_status_id_v(u32 r) | 417 | static inline u32 fifo_engine_status_id_v(u32 r) |
418 | { | 418 | { |
@@ -500,7 +500,7 @@ static inline u32 fifo_pbdma_status_r(u32 i) | |||
500 | } | 500 | } |
501 | static inline u32 fifo_pbdma_status__size_1_v(void) | 501 | static inline u32 fifo_pbdma_status__size_1_v(void) |
502 | { | 502 | { |
503 | return 0x00000001; | 503 | return 0x00000003; |
504 | } | 504 | } |
505 | static inline u32 fifo_pbdma_status_id_v(u32 r) | 505 | static inline u32 fifo_pbdma_status_id_v(u32 r) |
506 | { | 506 | { |
@@ -600,11 +600,11 @@ static inline u32 fifo_replay_fault_buffer_size_r(void) | |||
600 | } | 600 | } |
601 | static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) | 601 | static inline u32 fifo_replay_fault_buffer_size_hw_f(u32 v) |
602 | { | 602 | { |
603 | return (v & 0x1ff) << 0; | 603 | return (v & 0x3ff) << 0; |
604 | } | 604 | } |
605 | static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) | 605 | static inline u32 fifo_replay_fault_buffer_size_hw_entries_v(void) |
606 | { | 606 | { |
607 | return 0x000000c0; | 607 | return 0x00000140; |
608 | } | 608 | } |
609 | static inline u32 fifo_replay_fault_buffer_get_r(void) | 609 | static inline u32 fifo_replay_fault_buffer_get_r(void) |
610 | { | 610 | { |
@@ -612,7 +612,7 @@ static inline u32 fifo_replay_fault_buffer_get_r(void) | |||
612 | } | 612 | } |
613 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) | 613 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_f(u32 v) |
614 | { | 614 | { |
615 | return (v & 0x1ff) << 0; | 615 | return (v & 0x3ff) << 0; |
616 | } | 616 | } |
617 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) | 617 | static inline u32 fifo_replay_fault_buffer_get_offset_hw_init_v(void) |
618 | { | 618 | { |
@@ -624,7 +624,7 @@ static inline u32 fifo_replay_fault_buffer_put_r(void) | |||
624 | } | 624 | } |
625 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) | 625 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_f(u32 v) |
626 | { | 626 | { |
627 | return (v & 0x1ff) << 0; | 627 | return (v & 0x3ff) << 0; |
628 | } | 628 | } |
629 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) | 629 | static inline u32 fifo_replay_fault_buffer_put_offset_hw_init_v(void) |
630 | { | 630 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h index 955626a6..8c324225 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gmmu_gv11b.h | |||
@@ -242,6 +242,14 @@ static inline u32 gmmu_new_pte_address_sys_w(void) | |||
242 | { | 242 | { |
243 | return 0; | 243 | return 0; |
244 | } | 244 | } |
245 | static inline u32 gmmu_new_pte_address_vid_f(u32 v) | ||
246 | { | ||
247 | return (v & 0xffffff) << 8; | ||
248 | } | ||
249 | static inline u32 gmmu_new_pte_address_vid_w(void) | ||
250 | { | ||
251 | return 0; | ||
252 | } | ||
245 | static inline u32 gmmu_new_pte_vol_w(void) | 253 | static inline u32 gmmu_new_pte_vol_w(void) |
246 | { | 254 | { |
247 | return 0; | 255 | return 0; |
@@ -1110,7 +1118,7 @@ static inline u32 gmmu_pte_kind_c32_ms2_2cbr_v(void) | |||
1110 | { | 1118 | { |
1111 | return 0x000000de; | 1119 | return 0x000000de; |
1112 | } | 1120 | } |
1113 | static inline u32 gmmu_pte_kind_c32_ms2_2cra_v(void) | 1121 | static inline u32 gmmu_pte_kind_c32_ms2_4cbra_v(void) |
1114 | { | 1122 | { |
1115 | return 0x000000cc; | 1123 | return 0x000000cc; |
1116 | } | 1124 | } |
@@ -1174,7 +1182,7 @@ static inline u32 gmmu_pte_kind_c64_ms2_2cbr_v(void) | |||
1174 | { | 1182 | { |
1175 | return 0x000000ec; | 1183 | return 0x000000ec; |
1176 | } | 1184 | } |
1177 | static inline u32 gmmu_pte_kind_c64_ms2_2cra_v(void) | 1185 | static inline u32 gmmu_pte_kind_c64_ms2_2cbra_v(void) |
1178 | { | 1186 | { |
1179 | return 0x000000cd; | 1187 | return 0x000000cd; |
1180 | } | 1188 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index a37ce6e7..6cfa33ea 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | |||
@@ -372,11 +372,11 @@ static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) | |||
372 | } | 372 | } |
373 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) | 373 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) |
374 | { | 374 | { |
375 | return 0x005046a4; | 375 | return 0x0050433c; |
376 | } | 376 | } |
377 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) | 377 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) |
378 | { | 378 | { |
379 | return 0x00419ea4; | 379 | return 0x00419b3c; |
380 | } | 380 | } |
381 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) | 381 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) |
382 | { | 382 | { |
@@ -468,7 +468,7 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_tex_subunits_status_r(void) | |||
468 | } | 468 | } |
469 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) | 469 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) |
470 | { | 470 | { |
471 | return 0x005046b8; | 471 | return 0x00504358; |
472 | } | 472 | } |
473 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) | 473 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) |
474 | { | 474 | { |
@@ -504,7 +504,7 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_ | |||
504 | } | 504 | } |
505 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) | 505 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) |
506 | { | 506 | { |
507 | return 0x005044a0; | 507 | return 0x0050436c; |
508 | } | 508 | } |
509 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) | 509 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) |
510 | { | 510 | { |
@@ -532,15 +532,15 @@ static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pe | |||
532 | } | 532 | } |
533 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) | 533 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) |
534 | { | 534 | { |
535 | return 0x005046bc; | 535 | return 0x0050435c; |
536 | } | 536 | } |
537 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) | 537 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) |
538 | { | 538 | { |
539 | return 0x005046c0; | 539 | return 0x00504360; |
540 | } | 540 | } |
541 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) | 541 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) |
542 | { | 542 | { |
543 | return 0x005044a4; | 543 | return 0x00504370; |
544 | } | 544 | } |
545 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) | 545 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) |
546 | { | 546 | { |
@@ -696,7 +696,7 @@ static inline u32 gr_fe_go_idle_timeout_count_disabled_f(void) | |||
696 | } | 696 | } |
697 | static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) | 697 | static inline u32 gr_fe_go_idle_timeout_count_prod_f(void) |
698 | { | 698 | { |
699 | return 0x7fffffff; | 699 | return 0x1800; |
700 | } | 700 | } |
701 | static inline u32 gr_fe_object_table_r(u32 i) | 701 | static inline u32 gr_fe_object_table_r(u32 i) |
702 | { | 702 | { |
@@ -706,9 +706,9 @@ static inline u32 gr_fe_object_table_nvclass_v(u32 r) | |||
706 | { | 706 | { |
707 | return (r >> 0) & 0xffff; | 707 | return (r >> 0) & 0xffff; |
708 | } | 708 | } |
709 | static inline u32 gr_fe_tpc_fs_r(void) | 709 | static inline u32 gr_fe_tpc_fs_r(u32 i) |
710 | { | 710 | { |
711 | return 0x004041c4; | 711 | return 0x0040a200 + i*4; |
712 | } | 712 | } |
713 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) | 713 | static inline u32 gr_pri_mme_shadow_raw_index_r(void) |
714 | { | 714 | { |
@@ -1530,29 +1530,9 @@ static inline u32 gr_gpc0_gpccs_ctxsw_idlestate_r(void) | |||
1530 | { | 1530 | { |
1531 | return 0x00502420; | 1531 | return 0x00502420; |
1532 | } | 1532 | } |
1533 | static inline u32 gr_rstr2d_gpc_map0_r(void) | 1533 | static inline u32 gr_rstr2d_gpc_map_r(u32 i) |
1534 | { | 1534 | { |
1535 | return 0x0040780c; | 1535 | return 0x0040780c + i*4; |
1536 | } | ||
1537 | static inline u32 gr_rstr2d_gpc_map1_r(void) | ||
1538 | { | ||
1539 | return 0x00407810; | ||
1540 | } | ||
1541 | static inline u32 gr_rstr2d_gpc_map2_r(void) | ||
1542 | { | ||
1543 | return 0x00407814; | ||
1544 | } | ||
1545 | static inline u32 gr_rstr2d_gpc_map3_r(void) | ||
1546 | { | ||
1547 | return 0x00407818; | ||
1548 | } | ||
1549 | static inline u32 gr_rstr2d_gpc_map4_r(void) | ||
1550 | { | ||
1551 | return 0x0040781c; | ||
1552 | } | ||
1553 | static inline u32 gr_rstr2d_gpc_map5_r(void) | ||
1554 | { | ||
1555 | return 0x00407820; | ||
1556 | } | 1536 | } |
1557 | static inline u32 gr_rstr2d_map_table_cfg_r(void) | 1537 | static inline u32 gr_rstr2d_map_table_cfg_r(void) |
1558 | { | 1538 | { |
@@ -1656,7 +1636,7 @@ static inline u32 gr_pd_ab_dist_cfg2_token_limit_f(u32 v) | |||
1656 | } | 1636 | } |
1657 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) | 1637 | static inline u32 gr_pd_ab_dist_cfg2_token_limit_init_v(void) |
1658 | { | 1638 | { |
1659 | return 0x000001c0; | 1639 | return 0x00000380; |
1660 | } | 1640 | } |
1661 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) | 1641 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_f(u32 v) |
1662 | { | 1642 | { |
@@ -1668,7 +1648,7 @@ static inline u32 gr_pd_ab_dist_cfg2_state_limit_scc_bundle_granularity_v(void) | |||
1668 | } | 1648 | } |
1669 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) | 1649 | static inline u32 gr_pd_ab_dist_cfg2_state_limit_min_gpm_fifo_depths_v(void) |
1670 | { | 1650 | { |
1671 | return 0x00000182; | 1651 | return 0x00000302; |
1672 | } | 1652 | } |
1673 | static inline u32 gr_pd_dist_skip_table_r(u32 i) | 1653 | static inline u32 gr_pd_dist_skip_table_r(u32 i) |
1674 | { | 1654 | { |
@@ -2052,7 +2032,7 @@ static inline u32 gr_scc_bundle_cb_size_div_256b_f(u32 v) | |||
2052 | } | 2032 | } |
2053 | static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) | 2033 | static inline u32 gr_scc_bundle_cb_size_div_256b__prod_v(void) |
2054 | { | 2034 | { |
2055 | return 0x00000018; | 2035 | return 0x00000030; |
2056 | } | 2036 | } |
2057 | static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) | 2037 | static inline u32 gr_scc_bundle_cb_size_div_256b_byte_granularity_v(void) |
2058 | { | 2038 | { |
@@ -2352,19 +2332,19 @@ static inline u32 gr_gpc0_tpc0_pe_cfg_smid_value_f(u32 v) | |||
2352 | } | 2332 | } |
2353 | static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) | 2333 | static inline u32 gr_gpc0_tpc0_sm_cfg_r(void) |
2354 | { | 2334 | { |
2355 | return 0x00504698; | 2335 | return 0x00504608; |
2356 | } | 2336 | } |
2357 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) | 2337 | static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_f(u32 v) |
2358 | { | 2338 | { |
2359 | return (v & 0xffff) << 0; | 2339 | return (v & 0xffff) << 0; |
2360 | } | 2340 | } |
2361 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) | 2341 | static inline u32 gr_gpc0_tpc0_sm_cfg_tpc_id_v(u32 r) |
2362 | { | 2342 | { |
2363 | return (r >> 0) & 0xffff; | 2343 | return (r >> 0) & 0xffff; |
2364 | } | 2344 | } |
2365 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | 2345 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) |
2366 | { | 2346 | { |
2367 | return 0x0050469c; | 2347 | return 0x00504330; |
2368 | } | 2348 | } |
2369 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) | 2349 | static inline u32 gr_gpc0_tpc0_sm_arch_warp_count_v(u32 r) |
2370 | { | 2350 | { |
@@ -2404,11 +2384,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) | |||
2404 | } | 2384 | } |
2405 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) | 2385 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) |
2406 | { | 2386 | { |
2407 | return 0x00030000; | 2387 | return 0x00001000; |
2408 | } | 2388 | } |
2409 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) | 2389 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) |
2410 | { | 2390 | { |
2411 | return 0x00030a00; | 2391 | return 0x00001900; |
2412 | } | 2392 | } |
2413 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) | 2393 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) |
2414 | { | 2394 | { |
@@ -2452,11 +2432,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) | |||
2452 | } | 2432 | } |
2453 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) | 2433 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) |
2454 | { | 2434 | { |
2455 | return 0x00030000; | 2435 | return 0x00001000; |
2456 | } | 2436 | } |
2457 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) | 2437 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) |
2458 | { | 2438 | { |
2459 | return 0x00419b00; | 2439 | return 0x00419e00; |
2460 | } | 2440 | } |
2461 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) | 2441 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) |
2462 | { | 2442 | { |
@@ -2464,7 +2444,7 @@ static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v) | |||
2464 | } | 2444 | } |
2465 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) | 2445 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void) |
2466 | { | 2446 | { |
2467 | return 0x00419b04; | 2447 | return 0x00419e04; |
2468 | } | 2448 | } |
2469 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) | 2449 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void) |
2470 | { | 2450 | { |
@@ -2708,11 +2688,11 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_v(u32 r) | |||
2708 | } | 2688 | } |
2709 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) | 2689 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_v(void) |
2710 | { | 2690 | { |
2711 | return 0x00000018; | 2691 | return 0x00000030; |
2712 | } | 2692 | } |
2713 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) | 2693 | static inline u32 gr_gpcs_swdx_bundle_cb_size_div_256b_init_f(void) |
2714 | { | 2694 | { |
2715 | return 0x18; | 2695 | return 0x30; |
2716 | } | 2696 | } |
2717 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) | 2697 | static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_s(void) |
2718 | { | 2698 | { |
@@ -2748,7 +2728,7 @@ static inline u32 gr_gpcs_swdx_bundle_cb_size_valid_true_f(void) | |||
2748 | } | 2728 | } |
2749 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) | 2729 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_r(void) |
2750 | { | 2730 | { |
2751 | return 0x00500ee4; | 2731 | return 0x005001dc; |
2752 | } | 2732 | } |
2753 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) | 2733 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) |
2754 | { | 2734 | { |
@@ -2756,7 +2736,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_f(u32 v) | |||
2756 | } | 2736 | } |
2757 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) | 2737 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_default_v(void) |
2758 | { | 2738 | { |
2759 | return 0x00000250; | 2739 | return 0x00000170; |
2760 | } | 2740 | } |
2761 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) | 2741 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void) |
2762 | { | 2742 | { |
@@ -2764,7 +2744,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_size_256b_byte_granularity_v(void | |||
2764 | } | 2744 | } |
2765 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) | 2745 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_r(void) |
2766 | { | 2746 | { |
2767 | return 0x00500ee0; | 2747 | return 0x005001d8; |
2768 | } | 2748 | } |
2769 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) | 2749 | static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_f(u32 v) |
2770 | { | 2750 | { |
@@ -2776,7 +2756,7 @@ static inline u32 gr_gpc0_swdx_rm_spill_buffer_addr_39_8_align_bits_v(void) | |||
2776 | } | 2756 | } |
2777 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) | 2757 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_r(void) |
2778 | { | 2758 | { |
2779 | return 0x00418eec; | 2759 | return 0x004181e4; |
2780 | } | 2760 | } |
2781 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) | 2761 | static inline u32 gr_gpcs_swdx_beta_cb_ctrl_cbes_reserve_f(u32 v) |
2782 | { | 2762 | { |
@@ -2870,173 +2850,33 @@ static inline u32 gr_gpcs_setup_attrib_cb_base_valid_true_f(void) | |||
2870 | { | 2850 | { |
2871 | return 0x80000000; | 2851 | return 0x80000000; |
2872 | } | 2852 | } |
2873 | static inline u32 gr_crstr_gpc_map0_r(void) | 2853 | static inline u32 gr_crstr_gpc_map_r(u32 i) |
2874 | { | ||
2875 | return 0x00418b08; | ||
2876 | } | ||
2877 | static inline u32 gr_crstr_gpc_map0_tile0_f(u32 v) | ||
2878 | { | ||
2879 | return (v & 0x7) << 0; | ||
2880 | } | ||
2881 | static inline u32 gr_crstr_gpc_map0_tile1_f(u32 v) | ||
2882 | { | ||
2883 | return (v & 0x7) << 5; | ||
2884 | } | ||
2885 | static inline u32 gr_crstr_gpc_map0_tile2_f(u32 v) | ||
2886 | { | ||
2887 | return (v & 0x7) << 10; | ||
2888 | } | ||
2889 | static inline u32 gr_crstr_gpc_map0_tile3_f(u32 v) | ||
2890 | { | ||
2891 | return (v & 0x7) << 15; | ||
2892 | } | ||
2893 | static inline u32 gr_crstr_gpc_map0_tile4_f(u32 v) | ||
2894 | { | ||
2895 | return (v & 0x7) << 20; | ||
2896 | } | ||
2897 | static inline u32 gr_crstr_gpc_map0_tile5_f(u32 v) | ||
2898 | { | ||
2899 | return (v & 0x7) << 25; | ||
2900 | } | ||
2901 | static inline u32 gr_crstr_gpc_map1_r(void) | ||
2902 | { | ||
2903 | return 0x00418b0c; | ||
2904 | } | ||
2905 | static inline u32 gr_crstr_gpc_map1_tile6_f(u32 v) | ||
2906 | { | ||
2907 | return (v & 0x7) << 0; | ||
2908 | } | ||
2909 | static inline u32 gr_crstr_gpc_map1_tile7_f(u32 v) | ||
2910 | { | ||
2911 | return (v & 0x7) << 5; | ||
2912 | } | ||
2913 | static inline u32 gr_crstr_gpc_map1_tile8_f(u32 v) | ||
2914 | { | ||
2915 | return (v & 0x7) << 10; | ||
2916 | } | ||
2917 | static inline u32 gr_crstr_gpc_map1_tile9_f(u32 v) | ||
2918 | { | ||
2919 | return (v & 0x7) << 15; | ||
2920 | } | ||
2921 | static inline u32 gr_crstr_gpc_map1_tile10_f(u32 v) | ||
2922 | { | ||
2923 | return (v & 0x7) << 20; | ||
2924 | } | ||
2925 | static inline u32 gr_crstr_gpc_map1_tile11_f(u32 v) | ||
2926 | { | ||
2927 | return (v & 0x7) << 25; | ||
2928 | } | ||
2929 | static inline u32 gr_crstr_gpc_map2_r(void) | ||
2930 | { | ||
2931 | return 0x00418b10; | ||
2932 | } | ||
2933 | static inline u32 gr_crstr_gpc_map2_tile12_f(u32 v) | ||
2934 | { | ||
2935 | return (v & 0x7) << 0; | ||
2936 | } | ||
2937 | static inline u32 gr_crstr_gpc_map2_tile13_f(u32 v) | ||
2938 | { | ||
2939 | return (v & 0x7) << 5; | ||
2940 | } | ||
2941 | static inline u32 gr_crstr_gpc_map2_tile14_f(u32 v) | ||
2942 | { | ||
2943 | return (v & 0x7) << 10; | ||
2944 | } | ||
2945 | static inline u32 gr_crstr_gpc_map2_tile15_f(u32 v) | ||
2946 | { | ||
2947 | return (v & 0x7) << 15; | ||
2948 | } | ||
2949 | static inline u32 gr_crstr_gpc_map2_tile16_f(u32 v) | ||
2950 | { | ||
2951 | return (v & 0x7) << 20; | ||
2952 | } | ||
2953 | static inline u32 gr_crstr_gpc_map2_tile17_f(u32 v) | ||
2954 | { | ||
2955 | return (v & 0x7) << 25; | ||
2956 | } | ||
2957 | static inline u32 gr_crstr_gpc_map3_r(void) | ||
2958 | { | ||
2959 | return 0x00418b14; | ||
2960 | } | ||
2961 | static inline u32 gr_crstr_gpc_map3_tile18_f(u32 v) | ||
2962 | { | ||
2963 | return (v & 0x7) << 0; | ||
2964 | } | ||
2965 | static inline u32 gr_crstr_gpc_map3_tile19_f(u32 v) | ||
2966 | { | ||
2967 | return (v & 0x7) << 5; | ||
2968 | } | ||
2969 | static inline u32 gr_crstr_gpc_map3_tile20_f(u32 v) | ||
2970 | { | ||
2971 | return (v & 0x7) << 10; | ||
2972 | } | ||
2973 | static inline u32 gr_crstr_gpc_map3_tile21_f(u32 v) | ||
2974 | { | ||
2975 | return (v & 0x7) << 15; | ||
2976 | } | ||
2977 | static inline u32 gr_crstr_gpc_map3_tile22_f(u32 v) | ||
2978 | { | ||
2979 | return (v & 0x7) << 20; | ||
2980 | } | ||
2981 | static inline u32 gr_crstr_gpc_map3_tile23_f(u32 v) | ||
2982 | { | ||
2983 | return (v & 0x7) << 25; | ||
2984 | } | ||
2985 | static inline u32 gr_crstr_gpc_map4_r(void) | ||
2986 | { | ||
2987 | return 0x00418b18; | ||
2988 | } | ||
2989 | static inline u32 gr_crstr_gpc_map4_tile24_f(u32 v) | ||
2990 | { | ||
2991 | return (v & 0x7) << 0; | ||
2992 | } | ||
2993 | static inline u32 gr_crstr_gpc_map4_tile25_f(u32 v) | ||
2994 | { | ||
2995 | return (v & 0x7) << 5; | ||
2996 | } | ||
2997 | static inline u32 gr_crstr_gpc_map4_tile26_f(u32 v) | ||
2998 | { | ||
2999 | return (v & 0x7) << 10; | ||
3000 | } | ||
3001 | static inline u32 gr_crstr_gpc_map4_tile27_f(u32 v) | ||
3002 | { | 2854 | { |
3003 | return (v & 0x7) << 15; | 2855 | return 0x00418b08 + i*4; |
3004 | } | 2856 | } |
3005 | static inline u32 gr_crstr_gpc_map4_tile28_f(u32 v) | 2857 | static inline u32 gr_crstr_gpc_map_tile0_f(u32 v) |
3006 | { | 2858 | { |
3007 | return (v & 0x7) << 20; | 2859 | return (v & 0x1f) << 0; |
3008 | } | ||
3009 | static inline u32 gr_crstr_gpc_map4_tile29_f(u32 v) | ||
3010 | { | ||
3011 | return (v & 0x7) << 25; | ||
3012 | } | ||
3013 | static inline u32 gr_crstr_gpc_map5_r(void) | ||
3014 | { | ||
3015 | return 0x00418b1c; | ||
3016 | } | ||
3017 | static inline u32 gr_crstr_gpc_map5_tile30_f(u32 v) | ||
3018 | { | ||
3019 | return (v & 0x7) << 0; | ||
3020 | } | 2860 | } |
3021 | static inline u32 gr_crstr_gpc_map5_tile31_f(u32 v) | 2861 | static inline u32 gr_crstr_gpc_map_tile1_f(u32 v) |
3022 | { | 2862 | { |
3023 | return (v & 0x7) << 5; | 2863 | return (v & 0x1f) << 5; |
3024 | } | 2864 | } |
3025 | static inline u32 gr_crstr_gpc_map5_tile32_f(u32 v) | 2865 | static inline u32 gr_crstr_gpc_map_tile2_f(u32 v) |
3026 | { | 2866 | { |
3027 | return (v & 0x7) << 10; | 2867 | return (v & 0x1f) << 10; |
3028 | } | 2868 | } |
3029 | static inline u32 gr_crstr_gpc_map5_tile33_f(u32 v) | 2869 | static inline u32 gr_crstr_gpc_map_tile3_f(u32 v) |
3030 | { | 2870 | { |
3031 | return (v & 0x7) << 15; | 2871 | return (v & 0x1f) << 15; |
3032 | } | 2872 | } |
3033 | static inline u32 gr_crstr_gpc_map5_tile34_f(u32 v) | 2873 | static inline u32 gr_crstr_gpc_map_tile4_f(u32 v) |
3034 | { | 2874 | { |
3035 | return (v & 0x7) << 20; | 2875 | return (v & 0x1f) << 20; |
3036 | } | 2876 | } |
3037 | static inline u32 gr_crstr_gpc_map5_tile35_f(u32 v) | 2877 | static inline u32 gr_crstr_gpc_map_tile5_f(u32 v) |
3038 | { | 2878 | { |
3039 | return (v & 0x7) << 25; | 2879 | return (v & 0x1f) << 25; |
3040 | } | 2880 | } |
3041 | static inline u32 gr_crstr_map_table_cfg_r(void) | 2881 | static inline u32 gr_crstr_map_table_cfg_r(void) |
3042 | { | 2882 | { |
@@ -3050,159 +2890,39 @@ static inline u32 gr_crstr_map_table_cfg_num_entries_f(u32 v) | |||
3050 | { | 2890 | { |
3051 | return (v & 0xff) << 8; | 2891 | return (v & 0xff) << 8; |
3052 | } | 2892 | } |
3053 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_r(void) | 2893 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_r(u32 i) |
3054 | { | ||
3055 | return 0x00418980; | ||
3056 | } | ||
3057 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_0_f(u32 v) | ||
3058 | { | ||
3059 | return (v & 0x7) << 0; | ||
3060 | } | ||
3061 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_1_f(u32 v) | ||
3062 | { | ||
3063 | return (v & 0x7) << 4; | ||
3064 | } | ||
3065 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_2_f(u32 v) | ||
3066 | { | ||
3067 | return (v & 0x7) << 8; | ||
3068 | } | ||
3069 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_3_f(u32 v) | ||
3070 | { | ||
3071 | return (v & 0x7) << 12; | ||
3072 | } | ||
3073 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_4_f(u32 v) | ||
3074 | { | ||
3075 | return (v & 0x7) << 16; | ||
3076 | } | ||
3077 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_5_f(u32 v) | ||
3078 | { | ||
3079 | return (v & 0x7) << 20; | ||
3080 | } | ||
3081 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_6_f(u32 v) | ||
3082 | { | ||
3083 | return (v & 0x7) << 24; | ||
3084 | } | ||
3085 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map0_tile_7_f(u32 v) | ||
3086 | { | ||
3087 | return (v & 0x7) << 28; | ||
3088 | } | ||
3089 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_r(void) | ||
3090 | { | ||
3091 | return 0x00418984; | ||
3092 | } | ||
3093 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_8_f(u32 v) | ||
3094 | { | ||
3095 | return (v & 0x7) << 0; | ||
3096 | } | ||
3097 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_9_f(u32 v) | ||
3098 | { | ||
3099 | return (v & 0x7) << 4; | ||
3100 | } | ||
3101 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_10_f(u32 v) | ||
3102 | { | ||
3103 | return (v & 0x7) << 8; | ||
3104 | } | ||
3105 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_11_f(u32 v) | ||
3106 | { | ||
3107 | return (v & 0x7) << 12; | ||
3108 | } | ||
3109 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_12_f(u32 v) | ||
3110 | { | ||
3111 | return (v & 0x7) << 16; | ||
3112 | } | ||
3113 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_13_f(u32 v) | ||
3114 | { | ||
3115 | return (v & 0x7) << 20; | ||
3116 | } | ||
3117 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_14_f(u32 v) | ||
3118 | { | ||
3119 | return (v & 0x7) << 24; | ||
3120 | } | ||
3121 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map1_tile_15_f(u32 v) | ||
3122 | { | ||
3123 | return (v & 0x7) << 28; | ||
3124 | } | ||
3125 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_r(void) | ||
3126 | { | ||
3127 | return 0x00418988; | ||
3128 | } | ||
3129 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_16_f(u32 v) | ||
3130 | { | ||
3131 | return (v & 0x7) << 0; | ||
3132 | } | ||
3133 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_17_f(u32 v) | ||
3134 | { | ||
3135 | return (v & 0x7) << 4; | ||
3136 | } | ||
3137 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_18_f(u32 v) | ||
3138 | { | ||
3139 | return (v & 0x7) << 8; | ||
3140 | } | ||
3141 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_19_f(u32 v) | ||
3142 | { | ||
3143 | return (v & 0x7) << 12; | ||
3144 | } | ||
3145 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_20_f(u32 v) | ||
3146 | { | ||
3147 | return (v & 0x7) << 16; | ||
3148 | } | ||
3149 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_21_f(u32 v) | ||
3150 | { | ||
3151 | return (v & 0x7) << 20; | ||
3152 | } | ||
3153 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_22_f(u32 v) | ||
3154 | { | ||
3155 | return (v & 0x7) << 24; | ||
3156 | } | ||
3157 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_s(void) | ||
3158 | { | ||
3159 | return 3; | ||
3160 | } | ||
3161 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_f(u32 v) | ||
3162 | { | ||
3163 | return (v & 0x7) << 28; | ||
3164 | } | ||
3165 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_m(void) | ||
3166 | { | ||
3167 | return 0x7 << 28; | ||
3168 | } | ||
3169 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map2_tile_23_v(u32 r) | ||
3170 | { | ||
3171 | return (r >> 28) & 0x7; | ||
3172 | } | ||
3173 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_r(void) | ||
3174 | { | 2894 | { |
3175 | return 0x0041898c; | 2895 | return 0x00418980 + i*4; |
3176 | } | 2896 | } |
3177 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_24_f(u32 v) | 2897 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_0_f(u32 v) |
3178 | { | 2898 | { |
3179 | return (v & 0x7) << 0; | 2899 | return (v & 0x7) << 0; |
3180 | } | 2900 | } |
3181 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_25_f(u32 v) | 2901 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_1_f(u32 v) |
3182 | { | 2902 | { |
3183 | return (v & 0x7) << 4; | 2903 | return (v & 0x7) << 4; |
3184 | } | 2904 | } |
3185 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_26_f(u32 v) | 2905 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_2_f(u32 v) |
3186 | { | 2906 | { |
3187 | return (v & 0x7) << 8; | 2907 | return (v & 0x7) << 8; |
3188 | } | 2908 | } |
3189 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_27_f(u32 v) | 2909 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_3_f(u32 v) |
3190 | { | 2910 | { |
3191 | return (v & 0x7) << 12; | 2911 | return (v & 0x7) << 12; |
3192 | } | 2912 | } |
3193 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_28_f(u32 v) | 2913 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_4_f(u32 v) |
3194 | { | 2914 | { |
3195 | return (v & 0x7) << 16; | 2915 | return (v & 0x7) << 16; |
3196 | } | 2916 | } |
3197 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_29_f(u32 v) | 2917 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_5_f(u32 v) |
3198 | { | 2918 | { |
3199 | return (v & 0x7) << 20; | 2919 | return (v & 0x7) << 20; |
3200 | } | 2920 | } |
3201 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_30_f(u32 v) | 2921 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_6_f(u32 v) |
3202 | { | 2922 | { |
3203 | return (v & 0x7) << 24; | 2923 | return (v & 0x7) << 24; |
3204 | } | 2924 | } |
3205 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map3_tile_31_f(u32 v) | 2925 | static inline u32 gr_gpcs_zcull_sm_in_gpc_number_map_tile_7_f(u32 v) |
3206 | { | 2926 | { |
3207 | return (v & 0x7) << 28; | 2927 | return (v & 0x7) << 28; |
3208 | } | 2928 | } |
@@ -3210,14 +2930,6 @@ static inline u32 gr_gpcs_gpm_pd_cfg_r(void) | |||
3210 | { | 2930 | { |
3211 | return 0x00418c6c; | 2931 | return 0x00418c6c; |
3212 | } | 2932 | } |
3213 | static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_disable_f(void) | ||
3214 | { | ||
3215 | return 0x0; | ||
3216 | } | ||
3217 | static inline u32 gr_gpcs_gpm_pd_cfg_timeslice_mode_enable_f(void) | ||
3218 | { | ||
3219 | return 0x1; | ||
3220 | } | ||
3221 | static inline u32 gr_gpcs_gcc_pagepool_base_r(void) | 2933 | static inline u32 gr_gpcs_gcc_pagepool_base_r(void) |
3222 | { | 2934 | { |
3223 | return 0x00419004; | 2935 | return 0x00419004; |
@@ -3286,135 +2998,87 @@ static inline u32 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(void) | |||
3286 | { | 2998 | { |
3287 | return 0x10000000; | 2999 | return 0x10000000; |
3288 | } | 3000 | } |
3289 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(void) | 3001 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_r(void) |
3290 | { | 3002 | { |
3291 | return 0x00419e44; | 3003 | return 0x00419f28; |
3292 | } | 3004 | } |
3293 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_error_report_f(void) | 3005 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_error_report_f(void) |
3294 | { | 3006 | { |
3295 | return 0x2; | 3007 | return 0x2; |
3296 | } | 3008 | } |
3297 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_api_stack_error_report_f(void) | 3009 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_api_stack_error_report_f(void) |
3298 | { | 3010 | { |
3299 | return 0x4; | 3011 | return 0x4; |
3300 | } | 3012 | } |
3301 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_ret_empty_stack_error_report_f(void) | 3013 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_wrap_report_f(void) |
3302 | { | ||
3303 | return 0x8; | ||
3304 | } | ||
3305 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_wrap_report_f(void) | ||
3306 | { | 3014 | { |
3307 | return 0x10; | 3015 | return 0x10; |
3308 | } | 3016 | } |
3309 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_pc_report_f(void) | 3017 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_pc_report_f(void) |
3310 | { | 3018 | { |
3311 | return 0x20; | 3019 | return 0x20; |
3312 | } | 3020 | } |
3313 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_pc_overflow_report_f(void) | 3021 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_pc_overflow_report_f(void) |
3314 | { | 3022 | { |
3315 | return 0x40; | 3023 | return 0x40; |
3316 | } | 3024 | } |
3317 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_immc_addr_report_f(void) | 3025 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_reg_report_f(void) |
3318 | { | ||
3319 | return 0x80; | ||
3320 | } | ||
3321 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_reg_report_f(void) | ||
3322 | { | 3026 | { |
3323 | return 0x100; | 3027 | return 0x100; |
3324 | } | 3028 | } |
3325 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) | 3029 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_encoding_report_f(void) |
3326 | { | 3030 | { |
3327 | return 0x200; | 3031 | return 0x200; |
3328 | } | 3032 | } |
3329 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_sph_instr_combo_report_f(void) | 3033 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) |
3330 | { | ||
3331 | return 0x400; | ||
3332 | } | ||
3333 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param_report_f(void) | ||
3334 | { | 3034 | { |
3335 | return 0x800; | 3035 | return 0x800; |
3336 | } | 3036 | } |
3337 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_report_f(void) | 3037 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_reg_report_f(void) |
3338 | { | ||
3339 | return 0x1000; | ||
3340 | } | ||
3341 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_reg_report_f(void) | ||
3342 | { | 3038 | { |
3343 | return 0x2000; | 3039 | return 0x2000; |
3344 | } | 3040 | } |
3345 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_oor_addr_report_f(void) | 3041 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_oor_addr_report_f(void) |
3346 | { | 3042 | { |
3347 | return 0x4000; | 3043 | return 0x4000; |
3348 | } | 3044 | } |
3349 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_misaligned_addr_report_f(void) | 3045 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_misaligned_addr_report_f(void) |
3350 | { | 3046 | { |
3351 | return 0x8000; | 3047 | return 0x8000; |
3352 | } | 3048 | } |
3353 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) | 3049 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_addr_space_report_f(void) |
3354 | { | 3050 | { |
3355 | return 0x10000; | 3051 | return 0x10000; |
3356 | } | 3052 | } |
3357 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_illegal_instr_param2_report_f(void) | 3053 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) |
3358 | { | ||
3359 | return 0x20000; | ||
3360 | } | ||
3361 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_invalid_const_addr_ldc_report_f(void) | ||
3362 | { | 3054 | { |
3363 | return 0x40000; | 3055 | return 0x40000; |
3364 | } | 3056 | } |
3365 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_mmu_fault_report_f(void) | 3057 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_mmu_fault_report_f(void) |
3366 | { | 3058 | { |
3367 | return 0x800000; | 3059 | return 0x800000; |
3368 | } | 3060 | } |
3369 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_stack_overflow_report_f(void) | 3061 | static inline u32 gr_gpcs_tpcs_sm0_hww_warp_esr_report_mask_stack_overflow_report_f(void) |
3370 | { | 3062 | { |
3371 | return 0x400000; | 3063 | return 0x400000; |
3372 | } | 3064 | } |
3373 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_geometry_sm_error_report_f(void) | 3065 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_r(void) |
3374 | { | ||
3375 | return 0x80000; | ||
3376 | } | ||
3377 | static inline u32 gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_divergent_report_f(void) | ||
3378 | { | ||
3379 | return 0x100000; | ||
3380 | } | ||
3381 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r(void) | ||
3382 | { | ||
3383 | return 0x00419e4c; | ||
3384 | } | ||
3385 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_sm_to_sm_fault_report_f(void) | ||
3386 | { | 3066 | { |
3387 | return 0x1; | 3067 | return 0x00419f2c; |
3388 | } | ||
3389 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_l1_error_report_f(void) | ||
3390 | { | ||
3391 | return 0x2; | ||
3392 | } | 3068 | } |
3393 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) | 3069 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_multiple_warp_errors_report_f(void) |
3394 | { | 3070 | { |
3395 | return 0x4; | 3071 | return 0x4; |
3396 | } | 3072 | } |
3397 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_physical_stack_overflow_error_report_f(void) | 3073 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_int_report_f(void) |
3398 | { | ||
3399 | return 0x8; | ||
3400 | } | ||
3401 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_int_report_f(void) | ||
3402 | { | 3074 | { |
3403 | return 0x10; | 3075 | return 0x10; |
3404 | } | 3076 | } |
3405 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_sec_error_report_f(void) | 3077 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_bpt_pause_report_f(void) |
3406 | { | ||
3407 | return 0x20000000; | ||
3408 | } | ||
3409 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_ecc_ded_error_report_f(void) | ||
3410 | { | ||
3411 | return 0x40000000; | ||
3412 | } | ||
3413 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_bpt_pause_report_f(void) | ||
3414 | { | 3078 | { |
3415 | return 0x20; | 3079 | return 0x20; |
3416 | } | 3080 | } |
3417 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_single_step_complete_report_f(void) | 3081 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_report_mask_single_step_complete_report_f(void) |
3418 | { | 3082 | { |
3419 | return 0x40; | 3083 | return 0x40; |
3420 | } | 3084 | } |
@@ -3482,190 +3146,118 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_sm_pending_v(void) | |||
3482 | { | 3146 | { |
3483 | return 0x00000001; | 3147 | return 0x00000001; |
3484 | } | 3148 | } |
3485 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_r(void) | 3149 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_r(void) |
3486 | { | 3150 | { |
3487 | return 0x00504610; | 3151 | return 0x00504704; |
3488 | } | 3152 | } |
3489 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_m(void) | 3153 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_m(void) |
3490 | { | 3154 | { |
3491 | return 0x1 << 0; | 3155 | return 0x1 << 0; |
3492 | } | 3156 | } |
3493 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_v(u32 r) | 3157 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_v(u32 r) |
3494 | { | 3158 | { |
3495 | return (r >> 0) & 0x1; | 3159 | return (r >> 0) & 0x1; |
3496 | } | 3160 | } |
3497 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) | 3161 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v(void) |
3498 | { | 3162 | { |
3499 | return 0x00000001; | 3163 | return 0x00000001; |
3500 | } | 3164 | } |
3501 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) | 3165 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_off_v(void) |
3502 | { | 3166 | { |
3503 | return 0x00000000; | 3167 | return 0x00000000; |
3504 | } | 3168 | } |
3505 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | 3169 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f(void) |
3506 | { | 3170 | { |
3507 | return 0x80000000; | 3171 | return 0x80000000; |
3508 | } | 3172 | } |
3509 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | 3173 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_disable_f(void) |
3510 | { | 3174 | { |
3511 | return 0x0; | 3175 | return 0x0; |
3512 | } | 3176 | } |
3513 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) | 3177 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_enable_f(void) |
3514 | { | 3178 | { |
3515 | return 0x8; | 3179 | return 0x8; |
3516 | } | 3180 | } |
3517 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) | 3181 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_single_step_mode_disable_f(void) |
3518 | { | 3182 | { |
3519 | return 0x0; | 3183 | return 0x0; |
3520 | } | 3184 | } |
3521 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | 3185 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_control0_run_trigger_task_f(void) |
3522 | { | 3186 | { |
3523 | return 0x40000000; | 3187 | return 0x40000000; |
3524 | } | 3188 | } |
3525 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_m(void) | 3189 | static inline u32 gr_gpc0_tpc0_sm0_warp_valid_mask_r(void) |
3526 | { | ||
3527 | return 0x1 << 1; | ||
3528 | } | ||
3529 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) | ||
3530 | { | 3190 | { |
3531 | return (r >> 1) & 0x1; | 3191 | return 0x00504708; |
3532 | } | ||
3533 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) | ||
3534 | { | ||
3535 | return 0x0; | ||
3536 | } | ||
3537 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_m(void) | ||
3538 | { | ||
3539 | return 0x1 << 2; | ||
3540 | } | ||
3541 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) | ||
3542 | { | ||
3543 | return (r >> 2) & 0x1; | ||
3544 | } | ||
3545 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | ||
3546 | { | ||
3547 | return 0x0; | ||
3548 | } | ||
3549 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_warp_disable_v(void) | ||
3550 | { | ||
3551 | return 0x00000000; | ||
3552 | } | ||
3553 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_stop_on_any_sm_disable_v(void) | ||
3554 | { | ||
3555 | return 0x00000000; | ||
3556 | } | ||
3557 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | ||
3558 | { | ||
3559 | return 0x00504614; | ||
3560 | } | 3192 | } |
3561 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) | 3193 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_pause_mask_r(void) |
3562 | { | 3194 | { |
3563 | return 0x00504624; | 3195 | return 0x00504710; |
3564 | } | 3196 | } |
3565 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) | 3197 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_r(void) |
3566 | { | 3198 | { |
3567 | return 0x00504634; | 3199 | return 0x00504718; |
3568 | } | 3200 | } |
3569 | static inline u32 gr_gpcs_tpcs_sm_dbgr_bpt_pause_mask_r(void) | 3201 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_bpt_pause_mask_r(void) |
3570 | { | 3202 | { |
3571 | return 0x00419e24; | 3203 | return 0x00419f10; |
3572 | } | 3204 | } |
3573 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 3205 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_r(void) |
3574 | { | 3206 | { |
3575 | return 0x0050460c; | 3207 | return 0x00504700; |
3576 | } | 3208 | } |
3577 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) | 3209 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_sm_in_trap_mode_v(u32 r) |
3578 | { | 3210 | { |
3579 | return (r >> 0) & 0x1; | 3211 | return (r >> 0) & 0x1; |
3580 | } | 3212 | } |
3581 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) | 3213 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_v(u32 r) |
3582 | { | 3214 | { |
3583 | return (r >> 4) & 0x1; | 3215 | return (r >> 4) & 0x1; |
3584 | } | 3216 | } |
3585 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_true_v(void) | 3217 | static inline u32 gr_gpc0_tpc0_sm0_dbgr_status0_locked_down_true_v(void) |
3586 | { | 3218 | { |
3587 | return 0x00000001; | 3219 | return 0x00000001; |
3588 | } | 3220 | } |
3589 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_r(void) | 3221 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_r(void) |
3590 | { | 3222 | { |
3591 | return 0x00419e50; | 3223 | return 0x00419f34; |
3592 | } | 3224 | } |
3593 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_int_pending_f(void) | 3225 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_int_pending_f(void) |
3594 | { | 3226 | { |
3595 | return 0x10; | 3227 | return 0x10; |
3596 | } | 3228 | } |
3597 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_bpt_pause_pending_f(void) | 3229 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_bpt_pause_pending_f(void) |
3598 | { | 3230 | { |
3599 | return 0x20; | 3231 | return 0x20; |
3600 | } | 3232 | } |
3601 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f(void) | 3233 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_single_step_complete_pending_f(void) |
3602 | { | 3234 | { |
3603 | return 0x40; | 3235 | return 0x40; |
3604 | } | 3236 | } |
3605 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | 3237 | static inline u32 gr_gpcs_tpcs_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) |
3606 | { | ||
3607 | return 0x1; | ||
3608 | } | ||
3609 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) | ||
3610 | { | ||
3611 | return 0x2; | ||
3612 | } | ||
3613 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3614 | { | 3238 | { |
3615 | return 0x4; | 3239 | return 0x4; |
3616 | } | 3240 | } |
3617 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | 3241 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_r(void) |
3618 | { | ||
3619 | return 0x8; | ||
3620 | } | ||
3621 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3622 | { | 3242 | { |
3623 | return 0x80000000; | 3243 | return 0x00504734; |
3624 | } | ||
3625 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | ||
3626 | { | ||
3627 | return 0x00504650; | ||
3628 | } | 3244 | } |
3629 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f(void) | 3245 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f(void) |
3630 | { | 3246 | { |
3631 | return 0x10; | 3247 | return 0x10; |
3632 | } | 3248 | } |
3633 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_sec_error_pending_f(void) | 3249 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(void) |
3634 | { | ||
3635 | return 0x20000000; | ||
3636 | } | ||
3637 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_ecc_ded_error_pending_f(void) | ||
3638 | { | ||
3639 | return 0x40000000; | ||
3640 | } | ||
3641 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f(void) | ||
3642 | { | 3250 | { |
3643 | return 0x20; | 3251 | return 0x20; |
3644 | } | 3252 | } |
3645 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f(void) | 3253 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f(void) |
3646 | { | 3254 | { |
3647 | return 0x40; | 3255 | return 0x40; |
3648 | } | 3256 | } |
3649 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | 3257 | static inline u32 gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f(void) |
3650 | { | ||
3651 | return 0x1; | ||
3652 | } | ||
3653 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) | ||
3654 | { | ||
3655 | return 0x2; | ||
3656 | } | ||
3657 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3658 | { | 3258 | { |
3659 | return 0x4; | 3259 | return 0x4; |
3660 | } | 3260 | } |
3661 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3662 | { | ||
3663 | return 0x8; | ||
3664 | } | ||
3665 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3666 | { | ||
3667 | return 0x80000000; | ||
3668 | } | ||
3669 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | 3261 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) |
3670 | { | 3262 | { |
3671 | return 0x00504224; | 3263 | return 0x00504224; |
@@ -3682,45 +3274,45 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) | |||
3682 | { | 3274 | { |
3683 | return 0x100; | 3275 | return 0x100; |
3684 | } | 3276 | } |
3685 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_r(void) | 3277 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) |
3686 | { | 3278 | { |
3687 | return 0x00504648; | 3279 | return 0x00504730; |
3688 | } | 3280 | } |
3689 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_v(u32 r) | 3281 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_v(u32 r) |
3690 | { | 3282 | { |
3691 | return (r >> 0) & 0xffff; | 3283 | return (r >> 0) & 0xffff; |
3692 | } | 3284 | } |
3693 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_v(void) | 3285 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_v(void) |
3694 | { | 3286 | { |
3695 | return 0x00000000; | 3287 | return 0x00000000; |
3696 | } | 3288 | } |
3697 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) | 3289 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_error_none_f(void) |
3698 | { | 3290 | { |
3699 | return 0x0; | 3291 | return 0x0; |
3700 | } | 3292 | } |
3701 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m(void) | 3293 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_wrap_id_m(void) |
3702 | { | 3294 | { |
3703 | return 0x1 << 24; | 3295 | return 0xff << 16; |
3704 | } | 3296 | } |
3705 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(void) | 3297 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_m(void) |
3706 | { | 3298 | { |
3707 | return 0x7 << 25; | 3299 | return 0xf << 24; |
3708 | } | 3300 | } |
3709 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_none_f(void) | 3301 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_addr_error_type_none_f(void) |
3710 | { | 3302 | { |
3711 | return 0x0; | 3303 | return 0x0; |
3712 | } | 3304 | } |
3713 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) | 3305 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r(void) |
3714 | { | 3306 | { |
3715 | return 0x00504654; | 3307 | return 0x00504738; |
3716 | } | 3308 | } |
3717 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | 3309 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) |
3718 | { | 3310 | { |
3719 | return 0x00504770; | 3311 | return 0x005043a0; |
3720 | } | 3312 | } |
3721 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) | 3313 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_r(void) |
3722 | { | 3314 | { |
3723 | return 0x00419f70; | 3315 | return 0x00419ba0; |
3724 | } | 3316 | } |
3725 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) | 3317 | static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_m(void) |
3726 | { | 3318 | { |
@@ -3732,11 +3324,11 @@ static inline u32 gr_gpcs_tpcs_sm_halfctl_ctrl_sctl_read_quad_ctl_f(u32 v) | |||
3732 | } | 3324 | } |
3733 | static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) | 3325 | static inline u32 gr_gpc0_tpc0_sm_debug_sfe_control_r(void) |
3734 | { | 3326 | { |
3735 | return 0x0050477c; | 3327 | return 0x005043b0; |
3736 | } | 3328 | } |
3737 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) | 3329 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_r(void) |
3738 | { | 3330 | { |
3739 | return 0x00419f7c; | 3331 | return 0x00419bb0; |
3740 | } | 3332 | } |
3741 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) | 3333 | static inline u32 gr_gpcs_tpcs_sm_debug_sfe_control_read_half_ctl_m(void) |
3742 | { | 3334 | { |
@@ -3754,29 +3346,9 @@ static inline u32 gr_gpcs_tpcs_pes_vsc_vpc_fast_mode_switch_true_f(void) | |||
3754 | { | 3346 | { |
3755 | return 0x4; | 3347 | return 0x4; |
3756 | } | 3348 | } |
3757 | static inline u32 gr_ppcs_wwdx_map_gpc_map0_r(void) | 3349 | static inline u32 gr_ppcs_wwdx_map_gpc_map_r(u32 i) |
3758 | { | 3350 | { |
3759 | return 0x0041bf00; | 3351 | return 0x0041bf00 + i*4; |
3760 | } | ||
3761 | static inline u32 gr_ppcs_wwdx_map_gpc_map1_r(void) | ||
3762 | { | ||
3763 | return 0x0041bf04; | ||
3764 | } | ||
3765 | static inline u32 gr_ppcs_wwdx_map_gpc_map2_r(void) | ||
3766 | { | ||
3767 | return 0x0041bf08; | ||
3768 | } | ||
3769 | static inline u32 gr_ppcs_wwdx_map_gpc_map3_r(void) | ||
3770 | { | ||
3771 | return 0x0041bf0c; | ||
3772 | } | ||
3773 | static inline u32 gr_ppcs_wwdx_map_gpc_map4_r(void) | ||
3774 | { | ||
3775 | return 0x0041bf10; | ||
3776 | } | ||
3777 | static inline u32 gr_ppcs_wwdx_map_gpc_map5_r(void) | ||
3778 | { | ||
3779 | return 0x0041bf14; | ||
3780 | } | 3352 | } |
3781 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) | 3353 | static inline u32 gr_ppcs_wwdx_map_table_cfg_r(void) |
3782 | { | 3354 | { |
@@ -3798,10 +3370,6 @@ static inline u32 gr_ppcs_wwdx_map_table_cfg_normalized_shift_value_f(u32 v) | |||
3798 | { | 3370 | { |
3799 | return (v & 0x7) << 21; | 3371 | return (v & 0x7) << 21; |
3800 | } | 3372 | } |
3801 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff5_mod_value_f(u32 v) | ||
3802 | { | ||
3803 | return (v & 0x1f) << 24; | ||
3804 | } | ||
3805 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) | 3373 | static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_r(void) |
3806 | { | 3374 | { |
3807 | return 0x0041bfd4; | 3375 | return 0x0041bfd4; |
@@ -3810,33 +3378,25 @@ static inline u32 gr_gpcs_ppcs_wwdx_sm_num_rcp_conservative_f(u32 v) | |||
3810 | { | 3378 | { |
3811 | return (v & 0xffffff) << 0; | 3379 | return (v & 0xffffff) << 0; |
3812 | } | 3380 | } |
3813 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_r(void) | 3381 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_r(u32 i) |
3814 | { | ||
3815 | return 0x0041bfe4; | ||
3816 | } | ||
3817 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff6_mod_value_f(u32 v) | ||
3818 | { | 3382 | { |
3819 | return (v & 0x1f) << 0; | 3383 | return 0x0041bfb0 + i*4; |
3820 | } | 3384 | } |
3821 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff7_mod_value_f(u32 v) | 3385 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_0_mod_value_f(u32 v) |
3822 | { | 3386 | { |
3823 | return (v & 0x1f) << 5; | 3387 | return (v & 0xff) << 0; |
3824 | } | ||
3825 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff8_mod_value_f(u32 v) | ||
3826 | { | ||
3827 | return (v & 0x1f) << 10; | ||
3828 | } | 3388 | } |
3829 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff9_mod_value_f(u32 v) | 3389 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_1_mod_value_f(u32 v) |
3830 | { | 3390 | { |
3831 | return (v & 0x1f) << 15; | 3391 | return (v & 0xff) << 8; |
3832 | } | 3392 | } |
3833 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff10_mod_value_f(u32 v) | 3393 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_2_mod_value_f(u32 v) |
3834 | { | 3394 | { |
3835 | return (v & 0x1f) << 20; | 3395 | return (v & 0xff) << 16; |
3836 | } | 3396 | } |
3837 | static inline u32 gr_ppcs_wwdx_map_table_cfg2_coeff11_mod_value_f(u32 v) | 3397 | static inline u32 gr_ppcs_wwdx_map_table_cfg_coeff_3_mod_value_f(u32 v) |
3838 | { | 3398 | { |
3839 | return (v & 0x1f) << 25; | 3399 | return (v & 0xff) << 24; |
3840 | } | 3400 | } |
3841 | static inline u32 gr_bes_zrop_settings_r(void) | 3401 | static inline u32 gr_bes_zrop_settings_r(void) |
3842 | { | 3402 | { |
@@ -3884,107 +3444,75 @@ static inline u32 gr_zcull_subregion_qty_v(void) | |||
3884 | } | 3444 | } |
3885 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) | 3445 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel0_r(void) |
3886 | { | 3446 | { |
3887 | return 0x00504604; | 3447 | return 0x00504308; |
3888 | } | 3448 | } |
3889 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) | 3449 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control_sel1_r(void) |
3890 | { | 3450 | { |
3891 | return 0x00504608; | 3451 | return 0x0050430c; |
3892 | } | 3452 | } |
3893 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) | 3453 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(void) |
3894 | { | 3454 | { |
3895 | return 0x0050465c; | 3455 | return 0x00504318; |
3896 | } | 3456 | } |
3897 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) | 3457 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control1_r(void) |
3898 | { | 3458 | { |
3899 | return 0x00504660; | 3459 | return 0x00504320; |
3900 | } | 3460 | } |
3901 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) | 3461 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control2_r(void) |
3902 | { | 3462 | { |
3903 | return 0x00504664; | 3463 | return 0x00504324; |
3904 | } | 3464 | } |
3905 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) | 3465 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control3_r(void) |
3906 | { | 3466 | { |
3907 | return 0x00504668; | 3467 | return 0x00504328; |
3908 | } | 3468 | } |
3909 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) | 3469 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control4_r(void) |
3910 | { | 3470 | { |
3911 | return 0x0050466c; | 3471 | return 0x0050432c; |
3912 | } | 3472 | } |
3913 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) | 3473 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(void) |
3914 | { | 3474 | { |
3915 | return 0x00504658; | 3475 | return 0x0050431c; |
3916 | } | 3476 | } |
3917 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) | 3477 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_control_r(void) |
3918 | { | 3478 | { |
3919 | return 0x00504730; | 3479 | return 0x00504378; |
3920 | } | 3480 | } |
3921 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) | 3481 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_control_r(void) |
3922 | { | 3482 | { |
3923 | return 0x00504734; | 3483 | return 0x0050437c; |
3924 | } | 3484 | } |
3925 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) | 3485 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_control_r(void) |
3926 | { | 3486 | { |
3927 | return 0x00504738; | 3487 | return 0x00504380; |
3928 | } | 3488 | } |
3929 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) | 3489 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_control_r(void) |
3930 | { | 3490 | { |
3931 | return 0x0050473c; | 3491 | return 0x00504384; |
3932 | } | 3492 | } |
3933 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) | 3493 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter4_control_r(void) |
3934 | { | 3494 | { |
3935 | return 0x00504740; | 3495 | return 0x00504388; |
3936 | } | 3496 | } |
3937 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) | 3497 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter5_control_r(void) |
3938 | { | 3498 | { |
3939 | return 0x00504744; | 3499 | return 0x0050438c; |
3940 | } | 3500 | } |
3941 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) | 3501 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter6_control_r(void) |
3942 | { | 3502 | { |
3943 | return 0x00504748; | 3503 | return 0x00504390; |
3944 | } | 3504 | } |
3945 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) | 3505 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter7_control_r(void) |
3946 | { | 3506 | { |
3947 | return 0x0050474c; | 3507 | return 0x00504394; |
3948 | } | ||
3949 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status_s1_r(void) | ||
3950 | { | ||
3951 | return 0x00504678; | ||
3952 | } | 3508 | } |
3953 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_status1_r(void) | 3509 | static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status_s1_r(void) |
3954 | { | 3510 | { |
3955 | return 0x00504694; | 3511 | return 0x00504744; |
3956 | } | ||
3957 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s0_r(void) | ||
3958 | { | ||
3959 | return 0x005046f0; | ||
3960 | } | ||
3961 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter0_s1_r(void) | ||
3962 | { | ||
3963 | return 0x00504700; | ||
3964 | } | ||
3965 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s0_r(void) | ||
3966 | { | ||
3967 | return 0x005046f4; | ||
3968 | } | ||
3969 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter1_s1_r(void) | ||
3970 | { | ||
3971 | return 0x00504704; | ||
3972 | } | ||
3973 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s0_r(void) | ||
3974 | { | ||
3975 | return 0x005046f8; | ||
3976 | } | ||
3977 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter2_s1_r(void) | ||
3978 | { | ||
3979 | return 0x00504708; | ||
3980 | } | ||
3981 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s0_r(void) | ||
3982 | { | ||
3983 | return 0x005046fc; | ||
3984 | } | 3512 | } |
3985 | static inline u32 gr_pri_gpc0_tpc0_sm_dsm_perf_counter3_s1_r(void) | 3513 | static inline u32 gr_pri_gpc0_tpc0_sm0_dsm_perf_counter_status1_r(void) |
3986 | { | 3514 | { |
3987 | return 0x0050470c; | 3515 | return 0x00504750; |
3988 | } | 3516 | } |
3989 | static inline u32 gr_fe_pwr_mode_r(void) | 3517 | static inline u32 gr_fe_pwr_mode_r(void) |
3990 | { | 3518 | { |
@@ -4082,55 +3610,55 @@ static inline u32 gr_gpcs_mmu_num_active_ltcs_r(void) | |||
4082 | { | 3610 | { |
4083 | return 0x004188ac; | 3611 | return 0x004188ac; |
4084 | } | 3612 | } |
4085 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_r(void) | 3613 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_r(void) |
4086 | { | 3614 | { |
4087 | return 0x00419e10; | 3615 | return 0x00419f04; |
4088 | } | 3616 | } |
4089 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_f(u32 v) | 3617 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_f(u32 v) |
4090 | { | 3618 | { |
4091 | return (v & 0x1) << 0; | 3619 | return (v & 0x1) << 0; |
4092 | } | 3620 | } |
4093 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_debugger_mode_on_v(void) | 3621 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_debugger_mode_on_v(void) |
4094 | { | 3622 | { |
4095 | return 0x00000001; | 3623 | return 0x00000001; |
4096 | } | 3624 | } |
4097 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_m(void) | 3625 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_m(void) |
4098 | { | 3626 | { |
4099 | return 0x1 << 31; | 3627 | return 0x1 << 31; |
4100 | } | 3628 | } |
4101 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_v(u32 r) | 3629 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_v(u32 r) |
4102 | { | 3630 | { |
4103 | return (r >> 31) & 0x1; | 3631 | return (r >> 31) & 0x1; |
4104 | } | 3632 | } |
4105 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_enable_f(void) | 3633 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_enable_f(void) |
4106 | { | 3634 | { |
4107 | return 0x80000000; | 3635 | return 0x80000000; |
4108 | } | 3636 | } |
4109 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | 3637 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_stop_trigger_disable_f(void) |
4110 | { | 3638 | { |
4111 | return 0x0; | 3639 | return 0x0; |
4112 | } | 3640 | } |
4113 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) | 3641 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_m(void) |
4114 | { | 3642 | { |
4115 | return 0x1 << 3; | 3643 | return 0x1 << 3; |
4116 | } | 3644 | } |
4117 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) | 3645 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_enable_f(void) |
4118 | { | 3646 | { |
4119 | return 0x8; | 3647 | return 0x8; |
4120 | } | 3648 | } |
4121 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) | 3649 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_single_step_mode_disable_f(void) |
4122 | { | 3650 | { |
4123 | return 0x0; | 3651 | return 0x0; |
4124 | } | 3652 | } |
4125 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3653 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_m(void) |
4126 | { | 3654 | { |
4127 | return 0x1 << 30; | 3655 | return 0x1 << 30; |
4128 | } | 3656 | } |
4129 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_v(u32 r) | 3657 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_v(u32 r) |
4130 | { | 3658 | { |
4131 | return (r >> 30) & 0x1; | 3659 | return (r >> 30) & 0x1; |
4132 | } | 3660 | } |
4133 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_task_f(void) | 3661 | static inline u32 gr_gpcs_tpcs_sm0_dbgr_control0_run_trigger_task_f(void) |
4134 | { | 3662 | { |
4135 | return 0x40000000; | 3663 | return 0x40000000; |
4136 | } | 3664 | } |
@@ -4148,7 +3676,7 @@ static inline u32 gr_fe_gfxp_wfi_timeout_count_disabled_f(void) | |||
4148 | } | 3676 | } |
4149 | static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) | 3677 | static inline u32 gr_gpcs_tpcs_sm_texio_control_r(void) |
4150 | { | 3678 | { |
4151 | return 0x00419c84; | 3679 | return 0x00419bd8; |
4152 | } | 3680 | } |
4153 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) | 3681 | static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_f(u32 v) |
4154 | { | 3682 | { |
@@ -4164,7 +3692,7 @@ static inline u32 gr_gpcs_tpcs_sm_texio_control_oor_addr_check_mode_arm_63_48_ma | |||
4164 | } | 3692 | } |
4165 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) | 3693 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_r(void) |
4166 | { | 3694 | { |
4167 | return 0x00419f78; | 3695 | return 0x00419ba4; |
4168 | } | 3696 | } |
4169 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) | 3697 | static inline u32 gr_gpcs_tpcs_sm_disp_ctrl_re_suppress_m(void) |
4170 | { | 3698 | { |
@@ -4180,10 +3708,10 @@ static inline u32 gr_gpcs_tc_debug0_r(void) | |||
4180 | } | 3708 | } |
4181 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) | 3709 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_f(u32 v) |
4182 | { | 3710 | { |
4183 | return (v & 0xff) << 0; | 3711 | return (v & 0x1ff) << 0; |
4184 | } | 3712 | } |
4185 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) | 3713 | static inline u32 gr_gpcs_tc_debug0_limit_coalesce_buffer_size_m(void) |
4186 | { | 3714 | { |
4187 | return 0xff << 0; | 3715 | return 0x1ff << 0; |
4188 | } | 3716 | } |
4189 | #endif | 3717 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h index 2dbd759f..4c10852e 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ltc_gv11b.h | |||
@@ -570,12 +570,4 @@ static inline u32 ltc_ltc0_lts0_tstg_info_1_slices_per_l2_v(u32 r) | |||
570 | { | 570 | { |
571 | return (r >> 16) & 0x1f; | 571 | return (r >> 16) & 0x1f; |
572 | } | 572 | } |
573 | static inline u32 ltc_ltca_g_axi_pctrl_r(void) | ||
574 | { | ||
575 | return 0x00160000; | ||
576 | } | ||
577 | static inline u32 ltc_ltca_g_axi_pctrl_user_sid_f(u32 v) | ||
578 | { | ||
579 | return (v & 0xff) << 2; | ||
580 | } | ||
581 | #endif | 573 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index b3aaa7e6..259d366d 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | |||
@@ -72,7 +72,7 @@ static inline u32 pbdma_gp_base_r(u32 i) | |||
72 | } | 72 | } |
73 | static inline u32 pbdma_gp_base__size_1_v(void) | 73 | static inline u32 pbdma_gp_base__size_1_v(void) |
74 | { | 74 | { |
75 | return 0x00000001; | 75 | return 0x00000003; |
76 | } | 76 | } |
77 | static inline u32 pbdma_gp_base_offset_f(u32 v) | 77 | static inline u32 pbdma_gp_base_offset_f(u32 v) |
78 | { | 78 | { |
@@ -470,10 +470,6 @@ static inline u32 pbdma_intr_0_pbcrc_pending_f(void) | |||
470 | { | 470 | { |
471 | return 0x80000; | 471 | return 0x80000; |
472 | } | 472 | } |
473 | static inline u32 pbdma_intr_0_xbarconnect_pending_f(void) | ||
474 | { | ||
475 | return 0x100000; | ||
476 | } | ||
477 | static inline u32 pbdma_intr_0_method_pending_f(void) | 473 | static inline u32 pbdma_intr_0_method_pending_f(void) |
478 | { | 474 | { |
479 | return 0x200000; | 475 | return 0x200000; |
@@ -510,10 +506,6 @@ static inline u32 pbdma_intr_0_signature_pending_f(void) | |||
510 | { | 506 | { |
511 | return 0x80000000; | 507 | return 0x80000000; |
512 | } | 508 | } |
513 | static inline u32 pbdma_intr_0_syncpoint_illegal_pending_f(void) | ||
514 | { | ||
515 | return 0x10000000; | ||
516 | } | ||
517 | static inline u32 pbdma_intr_1_r(u32 i) | 509 | static inline u32 pbdma_intr_1_r(u32 i) |
518 | { | 510 | { |
519 | return 0x00040148 + i*8192; | 511 | return 0x00040148 + i*8192; |
@@ -566,38 +558,6 @@ static inline u32 pbdma_allowed_syncpoints_1_index_f(u32 v) | |||
566 | { | 558 | { |
567 | return (v & 0x7fff) << 0; | 559 | return (v & 0x7fff) << 0; |
568 | } | 560 | } |
569 | static inline u32 pbdma_syncpointa_r(u32 i) | ||
570 | { | ||
571 | return 0x000400a4 + i*8192; | ||
572 | } | ||
573 | static inline u32 pbdma_syncpointa_payload_v(u32 r) | ||
574 | { | ||
575 | return (r >> 0) & 0xffffffff; | ||
576 | } | ||
577 | static inline u32 pbdma_syncpointb_r(u32 i) | ||
578 | { | ||
579 | return 0x000400a8 + i*8192; | ||
580 | } | ||
581 | static inline u32 pbdma_syncpointb_op_v(u32 r) | ||
582 | { | ||
583 | return (r >> 0) & 0x1; | ||
584 | } | ||
585 | static inline u32 pbdma_syncpointb_op_wait_v(void) | ||
586 | { | ||
587 | return 0x00000000; | ||
588 | } | ||
589 | static inline u32 pbdma_syncpointb_wait_switch_v(u32 r) | ||
590 | { | ||
591 | return (r >> 4) & 0x1; | ||
592 | } | ||
593 | static inline u32 pbdma_syncpointb_wait_switch_en_v(void) | ||
594 | { | ||
595 | return 0x00000001; | ||
596 | } | ||
597 | static inline u32 pbdma_syncpointb_syncpt_index_v(u32 r) | ||
598 | { | ||
599 | return (r >> 8) & 0xfff; | ||
600 | } | ||
601 | static inline u32 pbdma_runlist_timeslice_r(u32 i) | 561 | static inline u32 pbdma_runlist_timeslice_r(u32 i) |
602 | { | 562 | { |
603 | return 0x000400f8 + i*8192; | 563 | return 0x000400f8 + i*8192; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h index 4d11fef4..836c014b 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_perf_gv11b.h | |||
@@ -52,7 +52,7 @@ | |||
52 | 52 | ||
53 | static inline u32 perf_pmasys_control_r(void) | 53 | static inline u32 perf_pmasys_control_r(void) |
54 | { | 54 | { |
55 | return 0x001b4000; | 55 | return 0x0024a000; |
56 | } | 56 | } |
57 | static inline u32 perf_pmasys_control_membuf_status_v(u32 r) | 57 | static inline u32 perf_pmasys_control_membuf_status_v(u32 r) |
58 | { | 58 | { |
@@ -84,7 +84,7 @@ static inline u32 perf_pmasys_control_membuf_clear_status_doit_f(void) | |||
84 | } | 84 | } |
85 | static inline u32 perf_pmasys_mem_block_r(void) | 85 | static inline u32 perf_pmasys_mem_block_r(void) |
86 | { | 86 | { |
87 | return 0x001b4070; | 87 | return 0x0024a070; |
88 | } | 88 | } |
89 | static inline u32 perf_pmasys_mem_block_base_f(u32 v) | 89 | static inline u32 perf_pmasys_mem_block_base_f(u32 v) |
90 | { | 90 | { |
@@ -148,7 +148,7 @@ static inline u32 perf_pmasys_mem_block_valid_false_f(void) | |||
148 | } | 148 | } |
149 | static inline u32 perf_pmasys_outbase_r(void) | 149 | static inline u32 perf_pmasys_outbase_r(void) |
150 | { | 150 | { |
151 | return 0x001b4074; | 151 | return 0x0024a074; |
152 | } | 152 | } |
153 | static inline u32 perf_pmasys_outbase_ptr_f(u32 v) | 153 | static inline u32 perf_pmasys_outbase_ptr_f(u32 v) |
154 | { | 154 | { |
@@ -156,7 +156,7 @@ static inline u32 perf_pmasys_outbase_ptr_f(u32 v) | |||
156 | } | 156 | } |
157 | static inline u32 perf_pmasys_outbaseupper_r(void) | 157 | static inline u32 perf_pmasys_outbaseupper_r(void) |
158 | { | 158 | { |
159 | return 0x001b4078; | 159 | return 0x0024a078; |
160 | } | 160 | } |
161 | static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) | 161 | static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) |
162 | { | 162 | { |
@@ -164,7 +164,7 @@ static inline u32 perf_pmasys_outbaseupper_ptr_f(u32 v) | |||
164 | } | 164 | } |
165 | static inline u32 perf_pmasys_outsize_r(void) | 165 | static inline u32 perf_pmasys_outsize_r(void) |
166 | { | 166 | { |
167 | return 0x001b407c; | 167 | return 0x0024a07c; |
168 | } | 168 | } |
169 | static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) | 169 | static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) |
170 | { | 170 | { |
@@ -172,7 +172,7 @@ static inline u32 perf_pmasys_outsize_numbytes_f(u32 v) | |||
172 | } | 172 | } |
173 | static inline u32 perf_pmasys_mem_bytes_r(void) | 173 | static inline u32 perf_pmasys_mem_bytes_r(void) |
174 | { | 174 | { |
175 | return 0x001b4084; | 175 | return 0x0024a084; |
176 | } | 176 | } |
177 | static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) | 177 | static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) |
178 | { | 178 | { |
@@ -180,7 +180,7 @@ static inline u32 perf_pmasys_mem_bytes_numbytes_f(u32 v) | |||
180 | } | 180 | } |
181 | static inline u32 perf_pmasys_mem_bump_r(void) | 181 | static inline u32 perf_pmasys_mem_bump_r(void) |
182 | { | 182 | { |
183 | return 0x001b4088; | 183 | return 0x0024a088; |
184 | } | 184 | } |
185 | static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) | 185 | static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) |
186 | { | 186 | { |
@@ -188,7 +188,7 @@ static inline u32 perf_pmasys_mem_bump_numbytes_f(u32 v) | |||
188 | } | 188 | } |
189 | static inline u32 perf_pmasys_enginestatus_r(void) | 189 | static inline u32 perf_pmasys_enginestatus_r(void) |
190 | { | 190 | { |
191 | return 0x001b40a4; | 191 | return 0x0024a0a4; |
192 | } | 192 | } |
193 | static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) | 193 | static inline u32 perf_pmasys_enginestatus_rbufempty_f(u32 v) |
194 | { | 194 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index e08c6854..3477c03e 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | |||
@@ -108,23 +108,23 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) | |||
108 | } | 108 | } |
109 | static inline u32 proj_host_num_engines_v(void) | 109 | static inline u32 proj_host_num_engines_v(void) |
110 | { | 110 | { |
111 | return 0x00000002; | 111 | return 0x00000004; |
112 | } | 112 | } |
113 | static inline u32 proj_host_num_pbdma_v(void) | 113 | static inline u32 proj_host_num_pbdma_v(void) |
114 | { | 114 | { |
115 | return 0x00000001; | 115 | return 0x00000003; |
116 | } | 116 | } |
117 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) | 117 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) |
118 | { | 118 | { |
119 | return 0x00000002; | 119 | return 0x00000004; |
120 | } | 120 | } |
121 | static inline u32 proj_scal_litter_num_fbps_v(void) | 121 | static inline u32 proj_scal_litter_num_fbps_v(void) |
122 | { | 122 | { |
123 | return 0x00000001; | 123 | return 0x00000002; |
124 | } | 124 | } |
125 | static inline u32 proj_scal_litter_num_fbpas_v(void) | 125 | static inline u32 proj_scal_litter_num_fbpas_v(void) |
126 | { | 126 | { |
127 | return 0x00000001; | 127 | return 0x00000004; |
128 | } | 128 | } |
129 | static inline u32 proj_scal_litter_num_gpcs_v(void) | 129 | static inline u32 proj_scal_litter_num_gpcs_v(void) |
130 | { | 130 | { |
@@ -132,7 +132,7 @@ static inline u32 proj_scal_litter_num_gpcs_v(void) | |||
132 | } | 132 | } |
133 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) | 133 | static inline u32 proj_scal_litter_num_pes_per_gpc_v(void) |
134 | { | 134 | { |
135 | return 0x00000001; | 135 | return 0x00000002; |
136 | } | 136 | } |
137 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) | 137 | static inline u32 proj_scal_litter_num_tpcs_per_pes_v(void) |
138 | { | 138 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h index 27ea4246..965f8663 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pwr_gv11b.h | |||
@@ -608,11 +608,11 @@ static inline u32 pwr_pmu_mutex_value_initial_lock_f(void) | |||
608 | } | 608 | } |
609 | static inline u32 pwr_pmu_queue_head_r(u32 i) | 609 | static inline u32 pwr_pmu_queue_head_r(u32 i) |
610 | { | 610 | { |
611 | return 0x0010a4a0 + i*4; | 611 | return 0x0010a800 + i*4; |
612 | } | 612 | } |
613 | static inline u32 pwr_pmu_queue_head__size_1_v(void) | 613 | static inline u32 pwr_pmu_queue_head__size_1_v(void) |
614 | { | 614 | { |
615 | return 0x00000004; | 615 | return 0x00000008; |
616 | } | 616 | } |
617 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) | 617 | static inline u32 pwr_pmu_queue_head_address_f(u32 v) |
618 | { | 618 | { |
@@ -624,11 +624,11 @@ static inline u32 pwr_pmu_queue_head_address_v(u32 r) | |||
624 | } | 624 | } |
625 | static inline u32 pwr_pmu_queue_tail_r(u32 i) | 625 | static inline u32 pwr_pmu_queue_tail_r(u32 i) |
626 | { | 626 | { |
627 | return 0x0010a4b0 + i*4; | 627 | return 0x0010a820 + i*4; |
628 | } | 628 | } |
629 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) | 629 | static inline u32 pwr_pmu_queue_tail__size_1_v(void) |
630 | { | 630 | { |
631 | return 0x00000004; | 631 | return 0x00000008; |
632 | } | 632 | } |
633 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) | 633 | static inline u32 pwr_pmu_queue_tail_address_f(u32 v) |
634 | { | 634 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 6ccbc266..c6f51acb 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | |||
@@ -148,7 +148,7 @@ static inline u32 ram_in_page_dir_base_lo_w(void) | |||
148 | } | 148 | } |
149 | static inline u32 ram_in_page_dir_base_hi_f(u32 v) | 149 | static inline u32 ram_in_page_dir_base_hi_f(u32 v) |
150 | { | 150 | { |
151 | return (v & 0xff) << 0; | 151 | return (v & 0xffffffff) << 0; |
152 | } | 152 | } |
153 | static inline u32 ram_in_page_dir_base_hi_w(void) | 153 | static inline u32 ram_in_page_dir_base_hi_w(void) |
154 | { | 154 | { |
@@ -354,14 +354,6 @@ static inline u32 ram_fc_allowed_syncpoints_w(void) | |||
354 | { | 354 | { |
355 | return 58; | 355 | return 58; |
356 | } | 356 | } |
357 | static inline u32 ram_fc_syncpointa_w(void) | ||
358 | { | ||
359 | return 41; | ||
360 | } | ||
361 | static inline u32 ram_fc_syncpointb_w(void) | ||
362 | { | ||
363 | return 42; | ||
364 | } | ||
365 | static inline u32 ram_fc_target_w(void) | 357 | static inline u32 ram_fc_target_w(void) |
366 | { | 358 | { |
367 | return 43; | 359 | return 43; |
@@ -444,46 +436,130 @@ static inline u32 ram_userd_gp_top_level_get_hi_w(void) | |||
444 | } | 436 | } |
445 | static inline u32 ram_rl_entry_size_v(void) | 437 | static inline u32 ram_rl_entry_size_v(void) |
446 | { | 438 | { |
439 | return 0x00000010; | ||
440 | } | ||
441 | static inline u32 ram_rl_entry_type_f(u32 v) | ||
442 | { | ||
443 | return (v & 0x1) << 0; | ||
444 | } | ||
445 | static inline u32 ram_rl_entry_type_channel_v(void) | ||
446 | { | ||
447 | return 0x00000000; | ||
448 | } | ||
449 | static inline u32 ram_rl_entry_type_tsg_v(void) | ||
450 | { | ||
451 | return 0x00000001; | ||
452 | } | ||
453 | static inline u32 ram_rl_entry_id_f(u32 v) | ||
454 | { | ||
455 | return (v & 0xfff) << 0; | ||
456 | } | ||
457 | static inline u32 ram_rl_entry_chan_runqueue_selector_f(u32 v) | ||
458 | { | ||
459 | return (v & 0x1) << 1; | ||
460 | } | ||
461 | static inline u32 ram_rl_entry_chan_inst_target_f(u32 v) | ||
462 | { | ||
463 | return (v & 0x3) << 4; | ||
464 | } | ||
465 | static inline u32 ram_rl_entry_chan_inst_target_target_sys_mem_ncoh_v(void) | ||
466 | { | ||
467 | return 0x00000003; | ||
468 | } | ||
469 | static inline u32 ram_rl_entry_chan_userd_target_f(u32 v) | ||
470 | { | ||
471 | return (v & 0x3) << 6; | ||
472 | } | ||
473 | static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_v(void) | ||
474 | { | ||
475 | return 0x00000000; | ||
476 | } | ||
477 | static inline u32 ram_rl_entry_chan_userd_target_target_vid_mem_nvlink_coh_v(void) | ||
478 | { | ||
479 | return 0x00000001; | ||
480 | } | ||
481 | static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_coh_v(void) | ||
482 | { | ||
483 | return 0x00000002; | ||
484 | } | ||
485 | static inline u32 ram_rl_entry_chan_userd_target_target_sys_mem_ncoh_v(void) | ||
486 | { | ||
487 | return 0x00000003; | ||
488 | } | ||
489 | static inline u32 ram_rl_entry_chan_userd_ptr_lo_f(u32 v) | ||
490 | { | ||
491 | return (v & 0xffffff) << 8; | ||
492 | } | ||
493 | static inline u32 ram_rl_entry_chan_userd_ptr_hi_f(u32 v) | ||
494 | { | ||
495 | return (v & 0xffffffff) << 0; | ||
496 | } | ||
497 | static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_inst_ptr_align_shift_v(void) | ||
498 | { | ||
499 | return 0x0000000c; | ||
500 | } | ||
501 | static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_ptr_align_shift_v(void) | ||
502 | { | ||
503 | return 0x00000008; | ||
504 | } | ||
505 | static inline u32 ram_rl_entry_chan_userd_ptr_hi_entry_chan_userd_align_shift_v(void) | ||
506 | { | ||
447 | return 0x00000008; | 507 | return 0x00000008; |
448 | } | 508 | } |
449 | static inline u32 ram_rl_entry_chid_f(u32 v) | 509 | static inline u32 ram_rl_entry_chid_f(u32 v) |
450 | { | 510 | { |
451 | return (v & 0xfff) << 0; | 511 | return (v & 0xfff) << 0; |
452 | } | 512 | } |
453 | static inline u32 ram_rl_entry_id_f(u32 v) | 513 | static inline u32 ram_rl_entry_chan_inst_ptr_lo_f(u32 v) |
454 | { | 514 | { |
455 | return (v & 0xfff) << 0; | 515 | return (v & 0xfffff) << 12; |
456 | } | 516 | } |
457 | static inline u32 ram_rl_entry_type_f(u32 v) | 517 | static inline u32 ram_rl_entry_chan_inst_ptr_hi_f(u32 v) |
458 | { | 518 | { |
459 | return (v & 0x1) << 13; | 519 | return (v & 0xffffffff) << 0; |
460 | } | 520 | } |
461 | static inline u32 ram_rl_entry_type_chid_f(void) | 521 | static inline u32 ram_rl_entry_tsg_vmid_f(u32 v) |
462 | { | 522 | { |
463 | return 0x0; | 523 | return (v & 0xff) << 4; |
464 | } | 524 | } |
465 | static inline u32 ram_rl_entry_type_tsg_f(void) | 525 | static inline u32 ram_rl_entry_tsg_timeslice_scale_f(u32 v) |
466 | { | 526 | { |
467 | return 0x2000; | 527 | return (v & 0xf) << 16; |
468 | } | 528 | } |
469 | static inline u32 ram_rl_entry_timeslice_scale_f(u32 v) | 529 | static inline u32 ram_rl_entry_tsg_timeslice_scale_entry_tsg_timeslice_scale_3_v(void) |
470 | { | 530 | { |
471 | return (v & 0xf) << 14; | 531 | return 0x00000003; |
472 | } | 532 | } |
473 | static inline u32 ram_rl_entry_timeslice_scale_3_f(void) | 533 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_f(u32 v) |
474 | { | 534 | { |
475 | return 0xc000; | 535 | return (v & 0xff) << 24; |
476 | } | 536 | } |
477 | static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v) | 537 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_128_v(void) |
478 | { | 538 | { |
479 | return (v & 0xff) << 18; | 539 | return 0x00000080; |
480 | } | 540 | } |
481 | static inline u32 ram_rl_entry_timeslice_timeout_128_f(void) | 541 | static inline u32 ram_rl_entry_tsg_timeslice_timeout_entry_tsg_timeslice_timeout_disable_v(void) |
482 | { | 542 | { |
483 | return 0x2000000; | 543 | return 0x00000000; |
484 | } | 544 | } |
485 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) | 545 | static inline u32 ram_rl_entry_tsg_length_f(u32 v) |
486 | { | 546 | { |
487 | return (v & 0x3f) << 26; | 547 | return (v & 0xff) << 0; |
548 | } | ||
549 | static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_init_v(void) | ||
550 | { | ||
551 | return 0x00000000; | ||
552 | } | ||
553 | static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_min_v(void) | ||
554 | { | ||
555 | return 0x00000001; | ||
556 | } | ||
557 | static inline u32 ram_rl_entry_tsg_length_entry_tsg_length_max_v(void) | ||
558 | { | ||
559 | return 0x00000080; | ||
560 | } | ||
561 | static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) | ||
562 | { | ||
563 | return (v & 0xfff) << 0; | ||
488 | } | 564 | } |
489 | #endif | 565 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h index 2c464d2c..a3cfcf91 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_therm_gv11b.h | |||
@@ -50,360 +50,4 @@ | |||
50 | #ifndef _hw_therm_gv11b_h_ | 50 | #ifndef _hw_therm_gv11b_h_ |
51 | #define _hw_therm_gv11b_h_ | 51 | #define _hw_therm_gv11b_h_ |
52 | 52 | ||
53 | static inline u32 therm_use_a_r(void) | ||
54 | { | ||
55 | return 0x00020798; | ||
56 | } | ||
57 | static inline u32 therm_use_a_ext_therm_0_enable_f(void) | ||
58 | { | ||
59 | return 0x1; | ||
60 | } | ||
61 | static inline u32 therm_use_a_ext_therm_1_enable_f(void) | ||
62 | { | ||
63 | return 0x2; | ||
64 | } | ||
65 | static inline u32 therm_use_a_ext_therm_2_enable_f(void) | ||
66 | { | ||
67 | return 0x4; | ||
68 | } | ||
69 | static inline u32 therm_evt_ext_therm_0_r(void) | ||
70 | { | ||
71 | return 0x00020700; | ||
72 | } | ||
73 | static inline u32 therm_evt_ext_therm_0_slow_factor_f(u32 v) | ||
74 | { | ||
75 | return (v & 0x3f) << 24; | ||
76 | } | ||
77 | static inline u32 therm_evt_ext_therm_0_slow_factor_init_v(void) | ||
78 | { | ||
79 | return 0x00000001; | ||
80 | } | ||
81 | static inline u32 therm_evt_ext_therm_0_mode_f(u32 v) | ||
82 | { | ||
83 | return (v & 0x3) << 30; | ||
84 | } | ||
85 | static inline u32 therm_evt_ext_therm_0_mode_normal_v(void) | ||
86 | { | ||
87 | return 0x00000000; | ||
88 | } | ||
89 | static inline u32 therm_evt_ext_therm_0_mode_inverted_v(void) | ||
90 | { | ||
91 | return 0x00000001; | ||
92 | } | ||
93 | static inline u32 therm_evt_ext_therm_0_mode_forced_v(void) | ||
94 | { | ||
95 | return 0x00000002; | ||
96 | } | ||
97 | static inline u32 therm_evt_ext_therm_0_mode_cleared_v(void) | ||
98 | { | ||
99 | return 0x00000003; | ||
100 | } | ||
101 | static inline u32 therm_evt_ext_therm_1_r(void) | ||
102 | { | ||
103 | return 0x00020704; | ||
104 | } | ||
105 | static inline u32 therm_evt_ext_therm_1_slow_factor_f(u32 v) | ||
106 | { | ||
107 | return (v & 0x3f) << 24; | ||
108 | } | ||
109 | static inline u32 therm_evt_ext_therm_1_slow_factor_init_v(void) | ||
110 | { | ||
111 | return 0x00000002; | ||
112 | } | ||
113 | static inline u32 therm_evt_ext_therm_1_mode_f(u32 v) | ||
114 | { | ||
115 | return (v & 0x3) << 30; | ||
116 | } | ||
117 | static inline u32 therm_evt_ext_therm_1_mode_normal_v(void) | ||
118 | { | ||
119 | return 0x00000000; | ||
120 | } | ||
121 | static inline u32 therm_evt_ext_therm_1_mode_inverted_v(void) | ||
122 | { | ||
123 | return 0x00000001; | ||
124 | } | ||
125 | static inline u32 therm_evt_ext_therm_1_mode_forced_v(void) | ||
126 | { | ||
127 | return 0x00000002; | ||
128 | } | ||
129 | static inline u32 therm_evt_ext_therm_1_mode_cleared_v(void) | ||
130 | { | ||
131 | return 0x00000003; | ||
132 | } | ||
133 | static inline u32 therm_evt_ext_therm_2_r(void) | ||
134 | { | ||
135 | return 0x00020708; | ||
136 | } | ||
137 | static inline u32 therm_evt_ext_therm_2_slow_factor_f(u32 v) | ||
138 | { | ||
139 | return (v & 0x3f) << 24; | ||
140 | } | ||
141 | static inline u32 therm_evt_ext_therm_2_slow_factor_init_v(void) | ||
142 | { | ||
143 | return 0x00000003; | ||
144 | } | ||
145 | static inline u32 therm_evt_ext_therm_2_mode_f(u32 v) | ||
146 | { | ||
147 | return (v & 0x3) << 30; | ||
148 | } | ||
149 | static inline u32 therm_evt_ext_therm_2_mode_normal_v(void) | ||
150 | { | ||
151 | return 0x00000000; | ||
152 | } | ||
153 | static inline u32 therm_evt_ext_therm_2_mode_inverted_v(void) | ||
154 | { | ||
155 | return 0x00000001; | ||
156 | } | ||
157 | static inline u32 therm_evt_ext_therm_2_mode_forced_v(void) | ||
158 | { | ||
159 | return 0x00000002; | ||
160 | } | ||
161 | static inline u32 therm_evt_ext_therm_2_mode_cleared_v(void) | ||
162 | { | ||
163 | return 0x00000003; | ||
164 | } | ||
165 | static inline u32 therm_weight_1_r(void) | ||
166 | { | ||
167 | return 0x00020024; | ||
168 | } | ||
169 | static inline u32 therm_config1_r(void) | ||
170 | { | ||
171 | return 0x00020050; | ||
172 | } | ||
173 | static inline u32 therm_config2_r(void) | ||
174 | { | ||
175 | return 0x00020130; | ||
176 | } | ||
177 | static inline u32 therm_config2_slowdown_factor_extended_f(u32 v) | ||
178 | { | ||
179 | return (v & 0x1) << 24; | ||
180 | } | ||
181 | static inline u32 therm_config2_grad_enable_f(u32 v) | ||
182 | { | ||
183 | return (v & 0x1) << 31; | ||
184 | } | ||
185 | static inline u32 therm_gate_ctrl_r(u32 i) | ||
186 | { | ||
187 | return 0x00020200 + i*4; | ||
188 | } | ||
189 | static inline u32 therm_gate_ctrl_eng_clk_m(void) | ||
190 | { | ||
191 | return 0x3 << 0; | ||
192 | } | ||
193 | static inline u32 therm_gate_ctrl_eng_clk_run_f(void) | ||
194 | { | ||
195 | return 0x0; | ||
196 | } | ||
197 | static inline u32 therm_gate_ctrl_eng_clk_auto_f(void) | ||
198 | { | ||
199 | return 0x1; | ||
200 | } | ||
201 | static inline u32 therm_gate_ctrl_eng_clk_stop_f(void) | ||
202 | { | ||
203 | return 0x2; | ||
204 | } | ||
205 | static inline u32 therm_gate_ctrl_blk_clk_m(void) | ||
206 | { | ||
207 | return 0x3 << 2; | ||
208 | } | ||
209 | static inline u32 therm_gate_ctrl_blk_clk_run_f(void) | ||
210 | { | ||
211 | return 0x0; | ||
212 | } | ||
213 | static inline u32 therm_gate_ctrl_blk_clk_auto_f(void) | ||
214 | { | ||
215 | return 0x4; | ||
216 | } | ||
217 | static inline u32 therm_gate_ctrl_eng_pwr_m(void) | ||
218 | { | ||
219 | return 0x3 << 4; | ||
220 | } | ||
221 | static inline u32 therm_gate_ctrl_eng_pwr_auto_f(void) | ||
222 | { | ||
223 | return 0x10; | ||
224 | } | ||
225 | static inline u32 therm_gate_ctrl_eng_pwr_off_v(void) | ||
226 | { | ||
227 | return 0x00000002; | ||
228 | } | ||
229 | static inline u32 therm_gate_ctrl_eng_pwr_off_f(void) | ||
230 | { | ||
231 | return 0x20; | ||
232 | } | ||
233 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_f(u32 v) | ||
234 | { | ||
235 | return (v & 0x1f) << 8; | ||
236 | } | ||
237 | static inline u32 therm_gate_ctrl_eng_idle_filt_exp_m(void) | ||
238 | { | ||
239 | return 0x1f << 8; | ||
240 | } | ||
241 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_f(u32 v) | ||
242 | { | ||
243 | return (v & 0x7) << 13; | ||
244 | } | ||
245 | static inline u32 therm_gate_ctrl_eng_idle_filt_mant_m(void) | ||
246 | { | ||
247 | return 0x7 << 13; | ||
248 | } | ||
249 | static inline u32 therm_gate_ctrl_eng_delay_before_f(u32 v) | ||
250 | { | ||
251 | return (v & 0xf) << 16; | ||
252 | } | ||
253 | static inline u32 therm_gate_ctrl_eng_delay_before_m(void) | ||
254 | { | ||
255 | return 0xf << 16; | ||
256 | } | ||
257 | static inline u32 therm_gate_ctrl_eng_delay_after_f(u32 v) | ||
258 | { | ||
259 | return (v & 0xf) << 20; | ||
260 | } | ||
261 | static inline u32 therm_gate_ctrl_eng_delay_after_m(void) | ||
262 | { | ||
263 | return 0xf << 20; | ||
264 | } | ||
265 | static inline u32 therm_fecs_idle_filter_r(void) | ||
266 | { | ||
267 | return 0x00020288; | ||
268 | } | ||
269 | static inline u32 therm_fecs_idle_filter_value_m(void) | ||
270 | { | ||
271 | return 0xffffffff << 0; | ||
272 | } | ||
273 | static inline u32 therm_hubmmu_idle_filter_r(void) | ||
274 | { | ||
275 | return 0x0002028c; | ||
276 | } | ||
277 | static inline u32 therm_hubmmu_idle_filter_value_m(void) | ||
278 | { | ||
279 | return 0xffffffff << 0; | ||
280 | } | ||
281 | static inline u32 therm_clk_slowdown_r(u32 i) | ||
282 | { | ||
283 | return 0x00020160 + i*4; | ||
284 | } | ||
285 | static inline u32 therm_clk_slowdown_idle_factor_f(u32 v) | ||
286 | { | ||
287 | return (v & 0x3f) << 16; | ||
288 | } | ||
289 | static inline u32 therm_clk_slowdown_idle_factor_m(void) | ||
290 | { | ||
291 | return 0x3f << 16; | ||
292 | } | ||
293 | static inline u32 therm_clk_slowdown_idle_factor_v(u32 r) | ||
294 | { | ||
295 | return (r >> 16) & 0x3f; | ||
296 | } | ||
297 | static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void) | ||
298 | { | ||
299 | return 0x0; | ||
300 | } | ||
301 | static inline u32 therm_grad_stepping_table_r(u32 i) | ||
302 | { | ||
303 | return 0x000202c8 + i*4; | ||
304 | } | ||
305 | static inline u32 therm_grad_stepping_table_slowdown_factor0_f(u32 v) | ||
306 | { | ||
307 | return (v & 0x3f) << 0; | ||
308 | } | ||
309 | static inline u32 therm_grad_stepping_table_slowdown_factor0_m(void) | ||
310 | { | ||
311 | return 0x3f << 0; | ||
312 | } | ||
313 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by1p5_f(void) | ||
314 | { | ||
315 | return 0x1; | ||
316 | } | ||
317 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by2_f(void) | ||
318 | { | ||
319 | return 0x2; | ||
320 | } | ||
321 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by4_f(void) | ||
322 | { | ||
323 | return 0x6; | ||
324 | } | ||
325 | static inline u32 therm_grad_stepping_table_slowdown_factor0_fpdiv_by8_f(void) | ||
326 | { | ||
327 | return 0xe; | ||
328 | } | ||
329 | static inline u32 therm_grad_stepping_table_slowdown_factor1_f(u32 v) | ||
330 | { | ||
331 | return (v & 0x3f) << 6; | ||
332 | } | ||
333 | static inline u32 therm_grad_stepping_table_slowdown_factor1_m(void) | ||
334 | { | ||
335 | return 0x3f << 6; | ||
336 | } | ||
337 | static inline u32 therm_grad_stepping_table_slowdown_factor2_f(u32 v) | ||
338 | { | ||
339 | return (v & 0x3f) << 12; | ||
340 | } | ||
341 | static inline u32 therm_grad_stepping_table_slowdown_factor2_m(void) | ||
342 | { | ||
343 | return 0x3f << 12; | ||
344 | } | ||
345 | static inline u32 therm_grad_stepping_table_slowdown_factor3_f(u32 v) | ||
346 | { | ||
347 | return (v & 0x3f) << 18; | ||
348 | } | ||
349 | static inline u32 therm_grad_stepping_table_slowdown_factor3_m(void) | ||
350 | { | ||
351 | return 0x3f << 18; | ||
352 | } | ||
353 | static inline u32 therm_grad_stepping_table_slowdown_factor4_f(u32 v) | ||
354 | { | ||
355 | return (v & 0x3f) << 24; | ||
356 | } | ||
357 | static inline u32 therm_grad_stepping_table_slowdown_factor4_m(void) | ||
358 | { | ||
359 | return 0x3f << 24; | ||
360 | } | ||
361 | static inline u32 therm_grad_stepping0_r(void) | ||
362 | { | ||
363 | return 0x000202c0; | ||
364 | } | ||
365 | static inline u32 therm_grad_stepping0_feature_s(void) | ||
366 | { | ||
367 | return 1; | ||
368 | } | ||
369 | static inline u32 therm_grad_stepping0_feature_f(u32 v) | ||
370 | { | ||
371 | return (v & 0x1) << 0; | ||
372 | } | ||
373 | static inline u32 therm_grad_stepping0_feature_m(void) | ||
374 | { | ||
375 | return 0x1 << 0; | ||
376 | } | ||
377 | static inline u32 therm_grad_stepping0_feature_v(u32 r) | ||
378 | { | ||
379 | return (r >> 0) & 0x1; | ||
380 | } | ||
381 | static inline u32 therm_grad_stepping0_feature_enable_f(void) | ||
382 | { | ||
383 | return 0x1; | ||
384 | } | ||
385 | static inline u32 therm_grad_stepping1_r(void) | ||
386 | { | ||
387 | return 0x000202c4; | ||
388 | } | ||
389 | static inline u32 therm_grad_stepping1_pdiv_duration_f(u32 v) | ||
390 | { | ||
391 | return (v & 0x1ffff) << 0; | ||
392 | } | ||
393 | static inline u32 therm_clk_timing_r(u32 i) | ||
394 | { | ||
395 | return 0x000203c0 + i*4; | ||
396 | } | ||
397 | static inline u32 therm_clk_timing_grad_slowdown_f(u32 v) | ||
398 | { | ||
399 | return (v & 0x1) << 16; | ||
400 | } | ||
401 | static inline u32 therm_clk_timing_grad_slowdown_m(void) | ||
402 | { | ||
403 | return 0x1 << 16; | ||
404 | } | ||
405 | static inline u32 therm_clk_timing_grad_slowdown_enabled_f(void) | ||
406 | { | ||
407 | return 0x10000; | ||
408 | } | ||
409 | #endif | 53 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h index cb65cad8..2e2ff6ba 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_top_gv11b.h | |||
@@ -208,7 +208,7 @@ static inline u32 top_device_info_data_pri_base_align_v(void) | |||
208 | } | 208 | } |
209 | static inline u32 top_device_info_data_fault_id_enum_v(u32 r) | 209 | static inline u32 top_device_info_data_fault_id_enum_v(u32 r) |
210 | { | 210 | { |
211 | return (r >> 3) & 0x1f; | 211 | return (r >> 3) & 0x7f; |
212 | } | 212 | } |
213 | static inline u32 top_device_info_data_fault_id_v(u32 r) | 213 | static inline u32 top_device_info_data_fault_id_v(u32 r) |
214 | { | 214 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h new file mode 100644 index 00000000..8bcf163f --- /dev/null +++ b/drivers/gpu/nvgpu/gv11b/hw_usermode_gv11b.h | |||
@@ -0,0 +1,89 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_usermode_gv11b_h_ | ||
51 | #define _hw_usermode_gv11b_h_ | ||
52 | |||
53 | static inline u32 usermode_cfg0_r(void) | ||
54 | { | ||
55 | return 0x00810000; | ||
56 | } | ||
57 | static inline u32 usermode_cfg0_usermode_class_id_f(u32 v) | ||
58 | { | ||
59 | return (v & 0xffff) << 0; | ||
60 | } | ||
61 | static inline u32 usermode_cfg0_usermode_class_id_value_v(void) | ||
62 | { | ||
63 | return 0x0000c361; | ||
64 | } | ||
65 | static inline u32 usermode_time_0_r(void) | ||
66 | { | ||
67 | return 0x00810080; | ||
68 | } | ||
69 | static inline u32 usermode_time_0_nsec_f(u32 v) | ||
70 | { | ||
71 | return (v & 0x7ffffff) << 5; | ||
72 | } | ||
73 | static inline u32 usermode_time_1_r(void) | ||
74 | { | ||
75 | return 0x00810084; | ||
76 | } | ||
77 | static inline u32 usermode_time_1_nsec_f(u32 v) | ||
78 | { | ||
79 | return (v & 0x1fffffff) << 0; | ||
80 | } | ||
81 | static inline u32 usermode_notify_channel_pending_r(void) | ||
82 | { | ||
83 | return 0x00810090; | ||
84 | } | ||
85 | static inline u32 usermode_notify_channel_pending_id_f(u32 v) | ||
86 | { | ||
87 | return (v & 0xffffffff) << 0; | ||
88 | } | ||
89 | #endif | ||