gpu: nvgpu: gv11b: init perf related gr ops

Implement gv11b specific perf gr ops

JIRA GPUT19X-49
Bug 200311674

Change-Id: Ia65fe84df6e38e25f87d2c1b21c04b518c334d42
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1497402
GVS: Gerrit_Virtual_Submit
Reviewed-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Tested-by: Tushar Kashalikar <tkashalikar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

2 files changed, 238 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index f44c60b0..eefbdf3b 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3253,6 +3253,87 @@ static int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g,
         return 0;
 }
 
+static const u32 _num_ovr_perf_regs = 20;
+static u32 _ovr_perf_regs[20] = { 0, };
+
+static void gv11b_gr_init_ovr_sm_dsm_perf(void)
+{
+        if (_ovr_perf_regs[0] != 0)
+                return;
+
+        _ovr_perf_regs[0]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r();
+        _ovr_perf_regs[1]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r();
+        _ovr_perf_regs[2]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r();
+        _ovr_perf_regs[3]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r();
+        _ovr_perf_regs[4]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r();
+        _ovr_perf_regs[5]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r();
+        _ovr_perf_regs[6]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r();
+        _ovr_perf_regs[7]  = gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r();
+        _ovr_perf_regs[8]  = gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r();
+        _ovr_perf_regs[9]  = gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r();
+        _ovr_perf_regs[10] = gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r();
+        _ovr_perf_regs[11] = gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r();
+        _ovr_perf_regs[12] = gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r();
+        _ovr_perf_regs[13] = gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r();
+        _ovr_perf_regs[14] = gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r();
+        _ovr_perf_regs[15] = gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r();
+
+        _ovr_perf_regs[16] = gr_egpc0_etpc0_sm0_dsm_perf_counter4_r();
+        _ovr_perf_regs[17] = gr_egpc0_etpc0_sm0_dsm_perf_counter5_r();
+        _ovr_perf_regs[18] = gr_egpc0_etpc0_sm0_dsm_perf_counter6_r();
+        _ovr_perf_regs[19] = gr_egpc0_etpc0_sm0_dsm_perf_counter7_r();
+}
+
+/* Following are the blocks of registers that the ucode
+ * stores in the extended region.
+ */
+/* ==  ctxsw_extended_sm_dsm_perf_counter_register_stride_v() ? */
+static const u32 _num_sm_dsm_perf_regs;
+/* ==  ctxsw_extended_sm_dsm_perf_counter_control_register_stride_v() ?*/
+static const u32 _num_sm_dsm_perf_ctrl_regs = 2;
+static u32 *_sm_dsm_perf_regs;
+static u32 _sm_dsm_perf_ctrl_regs[2];
+
+static void gv11b_gr_init_sm_dsm_reg_info(void)
+{
+        if (_sm_dsm_perf_ctrl_regs[0] != 0)
+                return;
+
+        _sm_dsm_perf_ctrl_regs[0] =
+                              gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r();
+        _sm_dsm_perf_ctrl_regs[1] =
+                              gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r();
+}
+
+static void gv11b_gr_get_sm_dsm_perf_regs(struct gk20a *g,
+                                          u32 *num_sm_dsm_perf_regs,
+                                          u32 **sm_dsm_perf_regs,
+                                          u32 *perf_register_stride)
+{
+        *num_sm_dsm_perf_regs = _num_sm_dsm_perf_regs;
+        *sm_dsm_perf_regs = _sm_dsm_perf_regs;
+        *perf_register_stride =
+                ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v();
+}
+
+static void gv11b_gr_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
+                                               u32 *num_sm_dsm_perf_ctrl_regs,
+                                               u32 **sm_dsm_perf_ctrl_regs,
+                                               u32 *ctrl_register_stride)
+{
+        *num_sm_dsm_perf_ctrl_regs = _num_sm_dsm_perf_ctrl_regs;
+        *sm_dsm_perf_ctrl_regs = _sm_dsm_perf_ctrl_regs;
+        *ctrl_register_stride =
+                ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v();
+}
+
+static void gv11b_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs,
+                                               u32 **ovr_perf_regs)
+{
+        *num_ovr_perf_regs = _num_ovr_perf_regs;
+        *ovr_perf_regs = _ovr_perf_regs;
+}
+
 void gv11b_init_gr(struct gpu_ops *gops)
 {
         gp10b_init_gr(gops);
@@ -3337,4 +3418,9 @@ void gv11b_init_gr(struct gpu_ops *gops)
                         gr_gv11b_handle_tpc_sm_ecc_exception;
         gops->gr.handle_tpc_mpc_exception =
                         gr_gv11b_handle_tpc_mpc_exception;
+        gops->gr.init_ovr_sm_dsm_perf =  gv11b_gr_init_ovr_sm_dsm_perf;
+        gops->gr.init_sm_dsm_reg_info = gv11b_gr_init_sm_dsm_reg_info;
+        gops->gr.get_sm_dsm_perf_regs = gv11b_gr_get_sm_dsm_perf_regs;
+        gops->gr.get_sm_dsm_perf_ctrl_regs = gv11b_gr_get_sm_dsm_perf_ctrl_regs;
+        gops->gr.get_ovr_perf_regs = gv11b_gr_get_ovr_perf_regs;
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
index c9dbee52..153aef2f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h
@@ -3998,6 +3998,158 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void)
 {
         return 0x1 << 10;
 }
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void)
+{
+        return 0x00584200;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(void)
+{
+        return 0x00584204;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(void)
+{
+        return 0x00584208;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control1_r(void)
+{
+        return 0x00584210;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control2_r(void)
+{
+        return 0x00584214;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control3_r(void)
+{
+        return 0x00584218;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control4_r(void)
+{
+        return 0x0058421c;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control5_r(void)
+{
+        return 0x0058420c;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter0_control_r(void)
+{
+        return 0x00584220;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter1_control_r(void)
+{
+        return 0x00584224;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter2_control_r(void)
+{
+        return 0x00584228;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter3_control_r(void)
+{
+        return 0x0058422c;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter4_control_r(void)
+{
+        return 0x00584230;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter5_control_r(void)
+{
+        return 0x00584234;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter6_control_r(void)
+{
+        return 0x00584238;
+}
+static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter7_control_r(void)
+{
+        return 0x0058423c;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s0_r(void)
+{
+        return 0x00584600;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter_status_s1_r(void)
+{
+        return 0x00584604;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s0_r(void)
+{
+        return 0x00584624;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s0_r(void)
+{
+        return 0x00584628;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s0_r(void)
+{
+        return 0x0058462c;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s0_r(void)
+{
+        return 0x00584630;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s1_r(void)
+{
+        return 0x00584634;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s1_r(void)
+{
+        return 0x00584638;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s1_r(void)
+{
+        return 0x0058463c;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s1_r(void)
+{
+        return 0x00584640;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s2_r(void)
+{
+        return 0x00584644;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s2_r(void)
+{
+        return 0x00584648;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s2_r(void)
+{
+        return 0x0058464c;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s2_r(void)
+{
+        return 0x00584650;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter0_s3_r(void)
+{
+        return 0x00584654;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter1_s3_r(void)
+{
+        return 0x00584658;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter2_s3_r(void)
+{
+        return 0x0058465c;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter3_s3_r(void)
+{
+        return 0x00584660;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter4_r(void)
+{
+        return 0x00584614;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter5_r(void)
+{
+        return 0x00584618;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter6_r(void)
+{
+        return 0x0058461c;
+}
+static inline u32 gr_egpc0_etpc0_sm0_dsm_perf_counter7_r(void)
+{
+        return 0x00584620;
+}
 static inline u32 gr_fe_pwr_mode_r(void)
 {
         return 0x00404170;