diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-07-01 14:33:39 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-07-03 10:51:42 -0400 |
commit | 4cc1457703462f3743c05a866690d1748e7bd8e8 (patch) | |
tree | 382cdc8d20d92628fc60c47efc6bd61dcbed4107 /drivers | |
parent | e7ba93fefbc4df9663302d240f9fbd5967a75a3c (diff) |
gpu: nvgpu: Move clk bypass div code to clk init
Clock bypass divider was changed just before resetting priv ring.
Move the code to a new clk op instead so that it is executed only on
gk20a.
Change-Id: Ic8084a4a5fac23770f50b50f910ced2543ba0f28
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/764970
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 9 |
4 files changed, 16 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c index 44f8fb64..e10df6ac 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c | |||
@@ -629,6 +629,17 @@ static int gk20a_clk_register_export_ops(struct gk20a *g) | |||
629 | return ret; | 629 | return ret; |
630 | } | 630 | } |
631 | 631 | ||
632 | static void gk20a_clk_disable_slowboot(struct gk20a *g) | ||
633 | { | ||
634 | u32 data; | ||
635 | |||
636 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); | ||
637 | data = set_field(data, | ||
638 | trim_sys_gpc2clk_out_bypdiv_m(), | ||
639 | trim_sys_gpc2clk_out_bypdiv_f(0)); | ||
640 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); | ||
641 | } | ||
642 | |||
632 | static int gk20a_init_clk_support(struct gk20a *g) | 643 | static int gk20a_init_clk_support(struct gk20a *g) |
633 | { | 644 | { |
634 | struct clk_gk20a *clk = &g->clk; | 645 | struct clk_gk20a *clk = &g->clk; |
@@ -695,6 +706,7 @@ static int gk20a_suspend_clk_support(struct gk20a *g) | |||
695 | 706 | ||
696 | void gk20a_init_clk_ops(struct gpu_ops *gops) | 707 | void gk20a_init_clk_ops(struct gpu_ops *gops) |
697 | { | 708 | { |
709 | gops->clk.disable_slowboot = gk20a_clk_disable_slowboot; | ||
698 | gops->clk.init_clk_support = gk20a_init_clk_support; | 710 | gops->clk.init_clk_support = gk20a_init_clk_support; |
699 | gops->clk.suspend_clk_support = gk20a_suspend_clk_support; | 711 | gops->clk.suspend_clk_support = gk20a_suspend_clk_support; |
700 | } | 712 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index 5a25eecf..b1747987 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -780,6 +780,9 @@ static int gk20a_pm_finalize_poweron(struct device *dev) | |||
780 | bus_intr_en_0_pri_fecserr_m() | | 780 | bus_intr_en_0_pri_fecserr_m() | |
781 | bus_intr_en_0_pri_timeout_m()); | 781 | bus_intr_en_0_pri_timeout_m()); |
782 | 782 | ||
783 | if (g->ops.clk.disable_slowboot) | ||
784 | g->ops.clk.disable_slowboot(g); | ||
785 | |||
783 | gk20a_reset_priv_ring(g); | 786 | gk20a_reset_priv_ring(g); |
784 | 787 | ||
785 | /* TBD: move this after graphics init in which blcg/slcg is enabled. | 788 | /* TBD: move this after graphics init in which blcg/slcg is enabled. |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index fc2ed643..72f1178b 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -392,6 +392,7 @@ struct gpu_ops { | |||
392 | bool fecsbootstrapdone; | 392 | bool fecsbootstrapdone; |
393 | } pmu; | 393 | } pmu; |
394 | struct { | 394 | struct { |
395 | void (*disable_slowboot)(struct gk20a *g); | ||
395 | int (*init_clk_support)(struct gk20a *g); | 396 | int (*init_clk_support)(struct gk20a *g); |
396 | int (*suspend_clk_support)(struct gk20a *g); | 397 | int (*suspend_clk_support)(struct gk20a *g); |
397 | } clk; | 398 | } clk; |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index d11cff06..d19702bb 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -22,21 +22,12 @@ | |||
22 | #include "hw_mc_gk20a.h" | 22 | #include "hw_mc_gk20a.h" |
23 | #include "hw_pri_ringmaster_gk20a.h" | 23 | #include "hw_pri_ringmaster_gk20a.h" |
24 | #include "hw_pri_ringstation_sys_gk20a.h" | 24 | #include "hw_pri_ringstation_sys_gk20a.h" |
25 | #include "hw_trim_gk20a.h" | ||
26 | 25 | ||
27 | void gk20a_reset_priv_ring(struct gk20a *g) | 26 | void gk20a_reset_priv_ring(struct gk20a *g) |
28 | { | 27 | { |
29 | u32 data; | ||
30 | |||
31 | if (tegra_platform_is_linsim()) | 28 | if (tegra_platform_is_linsim()) |
32 | return; | 29 | return; |
33 | 30 | ||
34 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); | ||
35 | data = set_field(data, | ||
36 | trim_sys_gpc2clk_out_bypdiv_m(), | ||
37 | trim_sys_gpc2clk_out_bypdiv_f(0)); | ||
38 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); | ||
39 | |||
40 | gk20a_reset(g, mc_enable_priv_ring_enabled_f()); | 31 | gk20a_reset(g, mc_enable_priv_ring_enabled_f()); |
41 | 32 | ||
42 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) | 33 | if (g->ops.clock_gating.slcg_priring_load_gating_prod) |