gpu: nvgpu: fix address table for GPCS_TPC6 broadcast conversion

In gr_gk20a_create_priv_addr_table() and gv11b_gr_egpc_etpc_priv_addr_table(),
we create a table of unicast addresses from broadcast addresses
For GPC boardcast addresses like NV_PGRAPH_PRI_EGPCS_ETPC6_SM_*, we generate
the table assuming there are 7 TPCs in all the GPCs

But this is incorrect in some cases like GV100 where GPC0/1 have only 6 TPCs
And hence we end up generating registers which do not exist

Fix this by explicitly checking the number of TPCs and ensuring that address
generated is belongs to valid TPC

Bug 200400376
Jira NVGPU-564

Change-Id: I65d7d6cd7f0bf16171eb54ed71f1f3840ade3495
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1686806
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 24 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index e06d190e..ceb606e4 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -6353,6 +6353,7 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g,
 {
         int addr_type; /*enum ctxsw_addr_type */
         u32 gpc_num, tpc_num, ppc_num, be_num;
+        u32 priv_addr, gpc_addr;
         u32 broadcast_flags;
         u32 t;
         int err;
@@ -6404,10 +6405,18 @@ static int gr_gk20a_create_priv_addr_table(struct gk20a *g,
                                                                priv_addr_table, &t);
                                 if (err)
                                         return err;
-                        } else
-                                priv_addr_table[t++] =
-                                        pri_gpc_addr(g, pri_gpccs_addr_mask(addr),
-                                                     gpc_num);
+                        } else {
+                                priv_addr = pri_gpc_addr(g,
+                                                pri_gpccs_addr_mask(addr),
+                                                gpc_num);
+
+                                gpc_addr = pri_gpccs_addr_mask(priv_addr);
+                                tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr);
+                                if (tpc_num >= g->gr.gpc_tpc_count[gpc_num])
+                                        continue;
+
+                                priv_addr_table[t++] = priv_addr;
+                        }
                 }
         } else if (((addr_type == CTXSW_ADDR_TYPE_EGPC) ||
                         (addr_type == CTXSW_ADDR_TYPE_ETPC)) &&
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index e0c60efb..7f6d1906 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -3979,6 +3979,7 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
                  u32 gpc, u32 broadcast_flags, u32 *priv_addr_table, u32 *t)
 {
         u32 gpc_num, tpc_num;
+        u32 priv_addr, gpc_addr;
 
         nvgpu_log_info(g, "addr=0x%x", addr);
 
@@ -4017,10 +4018,16 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr,
                                         g, gpc_num, tpc_num, addr,
                                         priv_addr_table, t);
                         } else {
-                                priv_addr_table[*t] =
-                                        pri_egpc_addr(g,
-                                        pri_gpccs_addr_mask(addr),
-                                             gpc_num);
+                                priv_addr = pri_egpc_addr(g,
+                                                pri_gpccs_addr_mask(addr),
+                                                gpc_num);
+
+                                gpc_addr = pri_gpccs_addr_mask(priv_addr);
+                                tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr);
+                                if (tpc_num >= g->gr.gpc_tpc_count[gpc_num])
+                                        continue;
+
+                                priv_addr_table[*t] = priv_addr;
                                 nvgpu_log_info(g, "priv_addr_table[%d]:%#08x",
                                         *t, priv_addr_table[*t]);
                                 (*t)++;