gpu: nvgpu: add get_sm_no_lock_down_hww_global_esr_mask gr ops

This is required to take care of t19x changes to support
multiple SM

JIRA GPUT19X-75

Change-Id: Ifd2cb28ae442462fef1d2c4439baa817f00c2c9e
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514041
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 23 insertions, 13 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 70b1ac5f..a0a67332 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -295,6 +295,7 @@ struct gpu_ops {
                                                 u32 gpc, u32 tpc, u32 sm);
                 u32 (*get_sm_hww_global_esr)(struct gk20a *g,
                                                 u32 gpc, u32 tpc, u32 sm);
+                u32 (*get_sm_no_lock_down_hww_global_esr_mask)(struct gk20a *g);
                 void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc,
                                          u32 *esr_sm_sel);
                 int (*handle_sm_exception)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index b714b2e2..d325f794 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5527,16 +5527,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
         bool disable_sm_exceptions = true;
         u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc);
         bool sm_debugger_attached;
-        u32 global_esr, warp_esr;
-
-        /* these three interrupts don't require locking down the SM. They can
-         * be handled by usermode clients as they aren't fatal. Additionally,
-         * usermode clients may wish to allow some warps to execute while others
-         * are at breakpoints, as opposed to fatal errors where all warps should
-         * halt. */
-        u32 global_mask = gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()   |
-                          gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() |
-                          gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f();
+        u32 global_esr, warp_esr, global_mask;
 
         gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "");
 
@@ -5545,6 +5536,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
         global_esr = g->ops.gr.get_sm_hww_global_esr(g, gpc, tpc, sm);
         *hww_global_esr = global_esr;
         warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm);
+        global_mask = g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask(g);
 
         if (!sm_debugger_attached) {
                 nvgpu_err(g, "sm hww global 0x%08x warp 0x%08x",
@@ -8387,9 +8379,7 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct warpstate *w_state)
          * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp
          *    masks.
         */
-        global_mask = gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()   |
-                          gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() |
-                          gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f();
+        global_mask = g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask(g);
 
         /* Lock down all SMs */
         for (sm_id = 0; sm_id < gr->no_of_sm; sm_id++) {
@@ -8499,3 +8489,19 @@ u32 gk20a_gr_get_sm_hww_global_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm)
         return hww_global_esr;
 }
 
+u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g)
+{
+        /*
+         * These three interrupts don't require locking down the SM. They can
+         * be handled by usermode clients as they aren't fatal. Additionally,
+         * usermode clients may wish to allow some warps to execute while others
+         * are at breakpoints, as opposed to fatal errors where all warps should
+         * halt.
+         */
+        u32 global_esr_mask =
+                gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f() |
+                gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f() |
+                gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f();
+
+        return global_esr_mask;
+}
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 3dbf5697..8230ba72 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -541,6 +541,7 @@ void gr_gk20a_init_cg_mode(struct gk20a *g, u32 cgmode, u32 mode_config);
 bool gk20a_gr_sm_debugger_attached(struct gk20a *g);
 void gk20a_gr_clear_sm_hww(struct gk20a *g,
                                   u32 gpc, u32 tpc, u32 global_esr);
+u32 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask(struct gk20a *g);
 
 #define gr_gk20a_elpg_protected_call(g, func) \
         ({ \
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 3a1d579a..fecd487f 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1636,4 +1636,6 @@ void gm20b_init_gr(struct gpu_ops *gops)
         gops->gr.resume_all_sms = gk20a_gr_resume_all_sms;
         gops->gr.get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr;
         gops->gr.get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr;
+        gops->gr.get_sm_no_lock_down_hww_global_esr_mask =
+                         gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask;
 }