gpu: nvgpu: support CAU ctxsw list

CAU (Counter Aggregation Unit) registers might be split out from SMPC registers
and moved into their own list on some platforms

In gr_gk20a_init_ctx_vars_fw() add support to check if pm_cau list is available
If list is available, count will be set to non-zero here

In add_ctxsw_buffer_map_entries_gpcs(), parse the pm_cau list if count is
non-zero

Bug 2139870

Change-Id: Ia630e7d03481a6f927c6739d28ebfe49f221326f
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1733208
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Matthew Braun (SW-GPU) <matthewb@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 26 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
index f829cb3a..3f22a1b7 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
@@ -343,6 +343,14 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr)
                                 if (err)
                                         goto clean_up;
                                 break;
+                        case NETLIST_REGIONID_NVPERF_PMCAU:
+                                nvgpu_log_info(g, "NETLIST_REGIONID_NVPERF_PMCAU");
+                                err = gr_gk20a_alloc_load_netlist_aiv(g,
+                                        src, size,
+                                        &g->gr.ctx_vars.ctxsw_regs.pm_cau);
+                                if (err)
+                                        goto clean_up;
+                                break;
 
                         default:
                                 nvgpu_log_info(g, "unrecognized region %d skipped", i);
@@ -395,6 +403,7 @@ clean_up:
                 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_rop.l);
                 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_ucgpc.l);
                 nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.etpc.l);
+                nvgpu_kfree(g, g->gr.ctx_vars.ctxsw_regs.pm_cau.l);
                 nvgpu_release_firmware(g, netlist_fw);
                 err = -ENOENT;
         }
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
index d8fb8dcd..afc3e9df 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.h
@@ -105,6 +105,7 @@ union __max_name {
 #define NETLIST_REGIONID_CTXREG_PMROP           31
 #define NETLIST_REGIONID_CTXREG_PMUCGPC         32
 #define NETLIST_REGIONID_CTXREG_ETPC            33
+#define NETLIST_REGIONID_NVPERF_PMCAU           35
 
 struct netlist_region {
         u32 region_id;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 5fd0eb0c..b69618ae 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3130,6 +3130,7 @@ static void gk20a_remove_gr_support(struct gr_gk20a *gr)
         nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.gpc_router.l);
         nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.pm_ltc.l);
         nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.pm_fbpa.l);
+        nvgpu_kfree(g, gr->ctx_vars.ctxsw_regs.pm_cau.l);
 
         nvgpu_vfree(g, gr->ctx_vars.local_golden_image);
         gr->ctx_vars.local_golden_image = NULL;
@@ -7583,6 +7584,18 @@ static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
                                         count, offset, max_cnt, base, ~0))
                         return -EINVAL;
 
+                /* Counter Aggregation Unit, if available */
+                if (g->gr.ctx_vars.ctxsw_regs.pm_cau.count) {
+                        base = gpc_base + (gpc_stride * gpc_num)
+                                        + tpc_in_gpc_base;
+                        if (add_ctxsw_buffer_map_entries_subunits(map,
+                                        &g->gr.ctx_vars.ctxsw_regs.pm_cau,
+                                        count, offset, max_cnt, base, num_tpcs,
+                                        tpc_in_gpc_stride,
+                                        (tpc_in_gpc_stride - 1)))
+                                return -EINVAL;
+                }
+
                 *offset = ALIGN(*offset, 256);
         }
         return 0;
@@ -7648,6 +7661,8 @@ int gr_gk20a_add_ctxsw_reg_perf_pma(struct ctxsw_buf_offset_map_entry *map,
  *|  LIST_pm_ctx_reg_GPC             REGn TPC1  |
  *|  List_pm_ctx_reg_uc_GPC          REGn TPCn  |
  *|  LIST_nv_perf_ctx_reg_GPC                   |
+ *|  LIST_nv_perf_gpcrouter_ctx_reg             |
+ *|  LIST_nv_perf_ctx_reg_CAU                   |
  *|                                       ----  |--
  *|                            GPC1         .   |
  *|                                         .   |<----
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 8c21a714..49a69c26 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -319,6 +319,7 @@ struct gr_gk20a {
                         struct aiv_list_gk20a pm_rop;
                         struct aiv_list_gk20a pm_ucgpc;
                         struct aiv_list_gk20a etpc;
+                        struct aiv_list_gk20a pm_cau;
                 } ctxsw_regs;
                 u32 regs_base_index;
                 bool valid;