gpu: nvgpu: disable ELPG while accessing gr_gpcs_tpcs_sm_sch_macro_sched_r

bug 200139995

Any GR register access should disable ELPG and clock gating before
access and enable it back after it is done. Disable ELPG while tweaking
perf parameters in gk20a_alloc_obj_ctx.

Also output NV_PBUS_INTR_0 in case of interrupt (including fix to
display correct value on pbus isr).

Change-Id: I81d2eb4461e92fbb33db8554779f6566f6b002c1
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/835307
(cherry picked from commit 6acc35bd1bcc706fbde8d11521cf1d0f64a16fe4)
Reviewed-on: http://git-master/r/921299
(cherry picked from commit 73afd520445bb1f4757fd167b38289143fd46d80)
Reviewed-on: http://git-master/r/930040
(cherry picked from commit 7a784ebea0dd60a88469f51eaa61c33b356e499c)
Reviewed-on: http://git-master/r/1023529
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 54010a8e..fa2c61e1 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -552,6 +552,7 @@ void gk20a_pbus_isr(struct gk20a *g)
                         bus_intr_0_pri_timeout_m())) {
                 gk20a_err(dev_from_gk20a(g), "pmc_enable : 0x%x",
                         gk20a_readl(g, mc_enable_r()));
+                gk20a_err(dev_from_gk20a(g), "NV_PBUS_INTR_0 : 0x%x", val);
                 gk20a_err(&g->dev->dev,
                         "NV_PTIMER_PRI_TIMEOUT_SAVE_0: 0x%x\n",
                         gk20a_readl(g, timer_pri_timeout_save_0_r()));
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 187c9c0e..676dd6c9 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -2779,6 +2779,14 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a  *c,
                 u32 lockboost_mask;
                 u32 lockboost;
 
+                if (support_gk20a_pmu(g->dev)) {
+                        err = gk20a_pmu_disable_elpg(g);
+                        if (err) {
+                                gk20a_err(dev_from_gk20a(g),
+                                                "failed to set disable elpg");
+                        }
+                }
+
                 tex_lock_disable_mask =
                         gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m()         |
                         gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m()    |
@@ -2824,6 +2832,9 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a  *c,
                         gr_gk20a_ctx_patch_write_end(g, ch_ctx);
 
                 args->flags |= NVGPU_ALLOC_OBJ_FLAGS_LOCKBOOST_ZERO;
+
+                if (support_gk20a_pmu(g->dev))
+                        gk20a_pmu_enable_elpg(g);
         }
 
         /* init golden image, ELPG enabled after this is done */