gpu: nvgpu: clk arbiter skeleton

Add clock arbiter skeleton with support of clock sessions,
notifications on clock changes, request numbering, and asynchronous
handling of clock requests. Provides minimum behaviour to allow
unit tests implementation. Actual arbitration and clock settings
will be done separately. For now, dummy arbiter keeps last
requested target mhz. Actual arbiter may move to a lockless
implementation.

Jira DNVGPU-125

Change-Id: I6a8e443fb0d15dc5f1993e7260256d71acddd106
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1223476
(cherry picked from commit cb130825d84e4124d273bd443e2b62d493377461)
Reviewed-on: http://git-master/r/1243105
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

9 files changed, 618 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x
index bb19d595..a096a438 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x
@@ -38,11 +38,13 @@ nvgpu-y += \
         $(nvgpu-t18x)/clk/clk_domain.o \
         $(nvgpu-t18x)/clk/clk_prog.o \
         $(nvgpu-t18x)/clk/clk_vf_point.o \
+        $(nvgpu-t18x)/clk/clk_arb.o \
         $(nvgpu-t18x)/perf/vfe_var.o \
         $(nvgpu-t18x)/perf/vfe_equ.o \
         $(nvgpu-t18x)/perf/perf.o \
         $(nvgpu-t18x)/clk/clk.o \
         $(nvgpu-t18x)/gp106/clk_gp106.o \
+        $(nvgpu-t18x)/gp106/clk_arb_gp106.o \
         $(nvgpu-t18x)/gp106/gp106_gating_reglist.o \
         $(nvgpu-t18x)/gp106/xve_gp106.o \
         $(nvgpu-t18x)/gp106/therm_gp106.o \
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c
new file mode 100644
index 00000000..1d02c7d7
--- /dev/null
+++ b/drivers/gpu/nvgpu/clk/clk_arb.c
@@ -0,0 +1,387 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+
+#include <linux/cdev.h>
+#include <linux/file.h>
+#include <linux/anon_inodes.h>
+#include <linux/nvgpu.h>
+#include <linux/bitops.h>
+
+#include "clk/clk_arb.h"
+
+static int nvgpu_clk_arb_release_session_dev(struct inode *inode, struct file *filp);
+static unsigned int nvgpu_clk_arb_poll_session_dev(struct file *filp, poll_table *wait);
+
+static void nvgpu_clk_arb_run_arbiter_cb(struct work_struct *work);
+
+struct nvgpu_clk_arb {
+        struct mutex wlock;
+        struct mutex users_lock;
+        struct list_head users;
+        u32 gpc2clk_current_mhz;
+        u32 gpc2clk_target_mhz;
+        u32 gpc2clk_default_mhz;
+        u32 mclk_current_mhz;
+        u32 mclk_target_mhz;
+        u32 mclk_default_mhz;
+        atomic_t usercount;
+        struct work_struct update_fn_work;
+
+        atomic_t req_nr;        /* for allocations */
+        atomic_t last_req_nr;   /* last completed by arbiter */
+};
+
+struct nvgpu_clk_session {
+        struct gk20a *g;
+        int fd;
+        atomic_t req_nr;
+        struct kref refcount;
+        wait_queue_head_t readout_wq;
+        atomic_t poll_mask;
+        struct list_head user;
+        u32 gpc2clk_target_mhz;
+        u32 mclk_target_mhz;
+};
+
+const struct file_operations clk_dev_ops = {
+        .owner = THIS_MODULE,
+        .release = nvgpu_clk_arb_release_session_dev,
+        .poll = nvgpu_clk_arb_poll_session_dev,
+};
+
+int nvgpu_clk_arb_init_arbiter(struct gk20a *g)
+{
+        struct nvgpu_clk_arb *arb;
+        u16 default_mhz;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        if (!g->ops.clk_arb.get_arbiter_clk_domains)
+                return 0;
+
+        arb = kzalloc(sizeof(struct nvgpu_clk_arb), GFP_KERNEL);
+        if (!arb)
+                return -ENOMEM;
+
+        g->clk_arb = arb;
+
+        mutex_init(&arb->wlock);
+        mutex_init(&arb->users_lock);
+
+        err =  g->ops.clk_arb.get_arbiter_clk_default(g,
+                        NVGPU_GPU_CLK_DOMAIN_MCLK, &default_mhz);
+        if (err)
+                return -EINVAL;
+
+        arb->mclk_target_mhz = default_mhz;
+        arb->mclk_current_mhz = default_mhz;
+        arb->mclk_default_mhz = default_mhz;
+
+        err =  g->ops.clk_arb.get_arbiter_clk_default(g,
+                        NVGPU_GPU_CLK_DOMAIN_GPC2CLK, &default_mhz);
+        if (err)
+                return -EINVAL;
+
+        arb->gpc2clk_target_mhz = default_mhz;
+        arb->gpc2clk_current_mhz = default_mhz;
+        arb->gpc2clk_default_mhz = default_mhz;
+
+        atomic_set(&arb->usercount, 0);
+        atomic_set(&arb->req_nr, 0);
+        atomic_set(&arb->last_req_nr, 0);
+
+        INIT_LIST_HEAD(&arb->users);
+        INIT_WORK(&arb->update_fn_work, nvgpu_clk_arb_run_arbiter_cb);
+
+        return 0;
+}
+
+void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g)
+{
+        kfree(g->clk_arb);
+}
+
+
+int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
+                struct nvgpu_clk_session *session)
+{
+        struct file *file;
+        char *name;
+        int fd;
+        int err;
+
+        gk20a_dbg_fn("");
+
+        if (session->fd >= 0)
+                goto done;
+
+        fd = get_unused_fd_flags(O_RDWR);
+        if (fd < 0)
+                return fd;
+
+        name = kasprintf(GFP_KERNEL, "%s-clk-fd%d", dev_name(g->dev), fd);
+        file = anon_inode_getfile(name, &clk_dev_ops, session, O_RDWR);
+        kfree(name);
+        if (IS_ERR(file)) {
+                err = PTR_ERR(file);
+                goto clean_up_fd;
+        }
+
+        BUG_ON(file->private_data != session);
+
+        fd_install(fd, file);
+        kref_get(&session->refcount);
+
+        session->fd = fd;
+done:
+        return session->fd;
+
+clean_up_fd:
+        put_unused_fd(fd);
+
+        return err;
+}
+
+int nvgpu_clk_arb_init_session(struct gk20a *g,
+                struct nvgpu_clk_session **_session)
+{
+        struct nvgpu_clk_arb *arb = g->clk_arb;
+        struct nvgpu_clk_session *session = *(_session);
+
+        gk20a_dbg_fn("");
+
+        *_session = NULL;
+
+        if (!g->ops.clk_arb.get_arbiter_clk_domains)
+                return 0;
+
+        session = kzalloc(sizeof(struct nvgpu_clk_session), GFP_KERNEL);
+        if (!session)
+                return -ENOMEM;
+        session->g = g;
+        session->fd = -1;
+
+        kref_init(&session->refcount);
+        init_waitqueue_head(&session->readout_wq);
+
+        atomic_set(&session->poll_mask, 0);
+        atomic_set(&session->req_nr, 0);
+
+        mutex_lock(&arb->users_lock);
+        list_add_tail(&session->user, &arb->users);
+        mutex_unlock(&arb->users_lock);
+        atomic_inc(&arb->usercount);
+
+        mutex_lock(&arb->wlock);
+        session->mclk_target_mhz = arb->mclk_default_mhz;
+        session->gpc2clk_target_mhz = arb->gpc2clk_default_mhz;
+        mutex_unlock(&arb->wlock);
+
+        *_session = session;
+
+        return 0;
+}
+
+void nvgpu_clk_arb_free_session(struct kref *refcount)
+{
+        struct nvgpu_clk_session *session = container_of(refcount,
+                        struct nvgpu_clk_session, refcount);
+        struct gk20a *g = session->g;
+        struct nvgpu_clk_arb *arb = g->clk_arb;
+
+        mutex_lock(&arb->users_lock);
+        list_del_init(&session->user);
+        mutex_unlock(&arb->users_lock);
+
+        if (atomic_dec_and_test(&arb->usercount))
+                nvgpu_clk_arb_apply_session_constraints(g, NULL);
+
+        kfree(session);
+}
+
+void nvgpu_clk_arb_cleanup_session(struct gk20a *g,
+                struct nvgpu_clk_session *session)
+{
+        kref_put(&session->refcount, nvgpu_clk_arb_free_session);
+}
+
+static void nvgpu_clk_arb_run_arbiter_cb(struct work_struct *work)
+{
+        struct nvgpu_clk_arb *arb =
+                container_of(work, struct nvgpu_clk_arb, update_fn_work);
+        struct nvgpu_clk_session *session;
+
+        mutex_lock(&arb->wlock);
+
+        /* TODO: loop up higher or equal VF points */
+
+        arb->mclk_current_mhz = arb->mclk_target_mhz;
+        arb->gpc2clk_current_mhz = arb->gpc2clk_target_mhz;
+
+        /* TODO: actually program the clocks */
+
+        atomic_set(&arb->last_req_nr, atomic_read(&arb->req_nr));
+        mutex_unlock(&arb->wlock);
+
+        mutex_lock(&arb->users_lock);
+        list_for_each_entry(session, &arb->users, user) {
+                atomic_set(&session->poll_mask, POLLIN | POLLRDNORM);
+                wake_up_interruptible(&session->readout_wq);
+        }
+        mutex_unlock(&arb->users_lock);
+
+}
+
+void nvgpu_clk_arb_apply_session_constraints(struct gk20a *g,
+                struct nvgpu_clk_session *session)
+{
+        struct nvgpu_clk_arb *arb = g->clk_arb;
+
+        mutex_lock(&arb->wlock);
+        atomic_inc(&arb->req_nr);
+
+        /* TODO: arbitration between users.
+           For now, last session to run arbiter wins.
+         */
+
+        if (session) {
+                arb->mclk_target_mhz = session->mclk_target_mhz;
+                arb->gpc2clk_target_mhz = session->gpc2clk_target_mhz;
+
+                atomic_set(&session->req_nr, atomic_read(&arb->req_nr));
+        } else {
+                arb->mclk_target_mhz = arb->mclk_default_mhz;
+                arb->gpc2clk_target_mhz = arb->gpc2clk_default_mhz;
+        }
+        mutex_unlock(&arb->wlock);
+
+        schedule_work(&arb->update_fn_work);
+}
+
+static unsigned int nvgpu_clk_arb_poll_session_dev(struct file *filp, poll_table *wait)
+{
+        struct nvgpu_clk_session *session = filp->private_data;
+
+        gk20a_dbg_fn("");
+
+        poll_wait(filp, &session->readout_wq, wait);
+        return atomic_xchg(&session->poll_mask, 0);
+}
+
+static int nvgpu_clk_arb_release_session_dev(struct inode *inode, struct file *filp)
+{
+        struct nvgpu_clk_session *session = filp->private_data;
+        struct gk20a *g = session->g;
+
+        session->fd = -1;
+        nvgpu_clk_arb_cleanup_session(g, session);
+
+        return 0;
+}
+
+int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
+                u32 api_domain, u16 target_mhz)
+{
+
+        gk20a_dbg_fn("domain=0x%08x target_mhz=%u", api_domain, target_mhz);
+
+        switch (api_domain) {
+        case NVGPU_GPU_CLK_DOMAIN_MCLK:
+                session->mclk_target_mhz = target_mhz;
+                return 0;
+
+        case NVGPU_GPU_CLK_DOMAIN_GPC2CLK:
+                session->gpc2clk_target_mhz = target_mhz;
+                return 0;
+
+        default:
+                return -EINVAL;
+        }
+}
+
+int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
+                u32 api_domain, u16 *target_mhz)
+{
+        switch (api_domain) {
+        case NVGPU_GPU_CLK_DOMAIN_MCLK:
+                *target_mhz = session->mclk_target_mhz;
+                return 0;
+
+        case NVGPU_GPU_CLK_DOMAIN_GPC2CLK:
+                *target_mhz = session->gpc2clk_target_mhz;
+                return 0;
+
+        default:
+                *target_mhz = 0;
+                return -EINVAL;
+        }
+}
+
+int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
+                u32 api_domain, u16 *actual_mhz)
+{
+        struct nvgpu_clk_arb *arb = g->clk_arb;
+        int err = 0;
+
+        mutex_lock(&arb->wlock);
+        switch (api_domain) {
+        case NVGPU_GPU_CLK_DOMAIN_MCLK:
+                *actual_mhz = arb->mclk_current_mhz;
+                break;
+
+        case NVGPU_GPU_CLK_DOMAIN_GPC2CLK:
+                *actual_mhz = arb->gpc2clk_current_mhz;
+                break;
+
+        default:
+                *actual_mhz = 0;
+                err = -EINVAL;
+        }
+        mutex_unlock(&arb->wlock);
+
+        return err;
+}
+
+u32 nvgpu_clk_arb_get_arbiter_req_nr(struct gk20a *g)
+{
+        struct nvgpu_clk_arb *arb = g->clk_arb;
+
+        return atomic_read(&arb->last_req_nr);
+}
+
+int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+                u16 *min_mhz, u16 *max_mhz)
+{
+        return g->ops.clk_arb.get_arbiter_clk_range(g, api_domain,
+                        min_mhz, max_mhz);
+}
+
+u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
+{
+        return g->ops.clk_arb.get_arbiter_clk_domains(g);
+}
+
+u32 nvgpu_clk_arb_get_session_req_nr(struct gk20a *g,
+                struct nvgpu_clk_session *session)
+{
+        return atomic_read(&session->req_nr);
+}
+
+int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
+        u32 api_domain, u32 *max_points, u16 *fpoints)
+{
+        return (int)clk_domain_get_f_points(g, api_domain, max_points, fpoints);
+}
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.h b/drivers/gpu/nvgpu/clk/clk_arb.h
new file mode 100644
index 00000000..9981041b
--- /dev/null
+++ b/drivers/gpu/nvgpu/clk/clk_arb.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+
+#ifndef _CLK_ARB_H_
+#define _CLK_ARB_H_
+
+struct nvgpu_clk_arb;
+struct nvgpu_clk_session;
+
+int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
+
+int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+                u16 *min_mhz, u16 *max_mhz);
+
+int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
+                u32 api_domain, u16 *actual_mhz);
+
+int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
+        u32 api_domain, u32 *max_points, u16 *fpoints);
+
+u32 nvgpu_clk_arb_get_arbiter_req_nr(struct gk20a *g);
+
+u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g);
+
+void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g);
+
+int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
+                struct nvgpu_clk_session *session);
+
+int nvgpu_clk_arb_init_session(struct gk20a *g,
+                struct nvgpu_clk_session **_session);
+
+void nvgpu_clk_arb_cleanup_session(struct gk20a *g,
+                struct nvgpu_clk_session *session);
+
+void nvgpu_clk_arb_apply_session_constraints(struct gk20a *g,
+                struct nvgpu_clk_session *session);
+
+int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
+                u32 api_domain, u16 target_mhz);
+
+int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
+                u32 api_domain, u16 *target_mhz);
+
+u32 nvgpu_clk_arb_get_session_req_nr(struct gk20a *g,
+                struct nvgpu_clk_session *session);
+
+
+
+#endif /* _CLK_ARB_H_ */
+
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
new file mode 100644
index 00000000..d1cbb32b
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+
+#include "clk/clk_arb.h"
+#include "clk_arb_gp106.h"
+
+static u32 gp106_get_arbiter_clk_domains(struct gk20a *g)
+{
+        (void)g;
+        return (CTRL_CLK_DOMAIN_MCLK|CTRL_CLK_DOMAIN_GPC2CLK);
+}
+
+static int gp106_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
+                u16 *min_mhz, u16 *max_mhz)
+{
+        enum nv_pmu_clk_clkwhich clkwhich;
+        struct clk_set_info *p0_info;
+        struct clk_set_info *p5_info;
+
+        switch (api_domain) {
+        case CTRL_CLK_DOMAIN_MCLK:
+                clkwhich = clkwhich_mclk;
+                break;
+
+        case CTRL_CLK_DOMAIN_GPC2CLK:
+                clkwhich = clkwhich_gpc2clk;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        p5_info = pstate_get_clk_set_info(g,
+                        CTRL_PERF_PSTATE_P5, clkwhich);
+        if (!p5_info)
+                return -EINVAL;
+
+        p0_info = pstate_get_clk_set_info(g,
+                        CTRL_PERF_PSTATE_P0, clkwhich);
+        if (!p0_info)
+                return -EINVAL;
+
+        *min_mhz = p5_info->min_mhz;
+        *max_mhz = p0_info->max_mhz;
+
+        return 0;
+}
+
+static int gp106_get_arbiter_clk_default(struct gk20a *g, u32 api_domain,
+                u16 *default_mhz)
+{
+        enum nv_pmu_clk_clkwhich clkwhich;
+        struct clk_set_info *p0_info;
+
+        switch (api_domain) {
+        case CTRL_CLK_DOMAIN_MCLK:
+                clkwhich = clkwhich_mclk;
+                break;
+
+        case CTRL_CLK_DOMAIN_GPC2CLK:
+                clkwhich = clkwhich_gpc2clk;
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        p0_info = pstate_get_clk_set_info(g,
+                        CTRL_PERF_PSTATE_P0, clkwhich);
+        if (!p0_info)
+                return -EINVAL;
+
+        *default_mhz = p0_info->max_mhz;
+
+        return 0;
+}
+
+void gp106_init_clk_arb_ops(struct gpu_ops *gops)
+{
+        gops->clk_arb.get_arbiter_clk_domains = gp106_get_arbiter_clk_domains;
+        gops->clk_arb.get_arbiter_clk_range = gp106_get_arbiter_clk_range;
+        gops->clk_arb.get_arbiter_clk_default = gp106_get_arbiter_clk_default;
+}
diff --git a/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h
new file mode 100644
index 00000000..a9877199
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp106/clk_arb_gp106.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef CLK_ARB_GP106_H
+#define CLK_ARB_GP106_H
+
+void gp106_init_clk_arb_ops(struct gpu_ops *gops);
+
+#endif /* CLK_ARB_GP106_H */
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index 39c308a3..85dde69f 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -27,6 +27,7 @@
 #include "gk20a/gk20a.h"
 #include "hw_trim_gp106.h"
 #include "clk_gp106.h"
+#include "clk/clk_arb.h"
 
 #define gk20a_dbg_clk(fmt, arg...) \
         gk20a_dbg(gpu_dbg_clk, fmt, ##arg)
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 0f926be8..dc27cdae 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -37,6 +37,7 @@
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/pmu_gm20b.h"
 #include "gp106/clk_gp106.h"
+#include "gp106/clk_arb_gp106.h"
 
 #include "gp106/mm_gp106.h"
 #include "gp106/pmu_gp106.h"
@@ -210,6 +211,7 @@ int gp106_init_hal(struct gk20a *g)
         gk20a_init_debug_ops(gops);
         gk20a_init_dbg_session_ops(gops);
         gp106_init_clk_ops(gops);
+        gp106_init_clk_arb_ops(gops);
         gp106_init_regops(gops);
         gp10b_init_cde_ops(gops);
         gk20a_init_tsg_ops(gops);
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index e9b9775e..0dc15201 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -234,7 +234,7 @@ static int parse_pstate_entry_5x(struct gk20a *g,
         memset(pstate, 0, sizeof(struct pstate));
         pstate->super.type = CTRL_PERF_PSTATE_TYPE_3X;
         pstate->num = 0x0F - entry->pstate_level;
-        pstate->clklist.clksetinfolistsize = hdr->clock_entry_count;
+        pstate->clklist.num_info = hdr->clock_entry_count;
 
         gk20a_dbg_info("pstate P%u", pstate->num);
 
@@ -357,3 +357,41 @@ static int pstate_sw_setup(struct gk20a *g)
 done:
         return err;
 }
+
+static struct pstate *pstate_find(struct gk20a *g, u32 num)
+{
+        struct pstates *pstates = &(g->perf_pmu.pstatesobjs);
+        struct pstate *pstate;
+        u8 i;
+
+        gk20a_dbg_info("pstates = %p", pstates);
+
+        BOARDOBJGRP_FOR_EACH(&pstates->super.super,
+                        struct pstate *, pstate, i) {
+                gk20a_dbg_info("pstate=%p num=%u (looking for num=%u)",
+                                pstate, pstate->num, num);
+                if (pstate->num == num)
+                        return pstate;
+        }
+        return NULL;
+}
+
+struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g,
+                u32 pstate_num, enum nv_pmu_clk_clkwhich clkwhich)
+{
+        struct pstate *pstate = pstate_find(g, pstate_num);
+        struct clk_set_info *info;
+        u32 clkidx;
+
+        gk20a_dbg_info("pstate = %p", pstate);
+
+        if (!pstate)
+                return NULL;
+
+        for (clkidx = 0; clkidx < pstate->clklist.num_info; clkidx++) {
+                info = &pstate->clklist.clksetinfo[clkidx];
+                if (info->clkwhich == clkwhich)
+                        return info;
+        }
+        return NULL;
+}
diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h
index 11fa4c77..4ae72aa9 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.h
+++ b/drivers/gpu/nvgpu/pstate/pstate.h
@@ -20,6 +20,10 @@
 
 #define CTRL_PERF_PSTATE_TYPE_3X        0x3
 
+#define CTRL_PERF_PSTATE_P0             0
+#define CTRL_PERF_PSTATE_P5             5
+#define CTRL_PERF_PSTATE_P8             8
+
 #define CLK_SET_INFO_MAX_SIZE           (32)
 
 struct clk_set_info {
@@ -30,7 +34,7 @@ struct clk_set_info {
 };
 
 struct clk_set_info_list {
-        u32 clksetinfolistsize;
+        u32 num_info;
         struct clk_set_info clksetinfo[CLK_SET_INFO_MAX_SIZE];
 };
 
@@ -48,4 +52,7 @@ struct pstates {
 int gk20a_init_pstate_support(struct gk20a *g);
 int gk20a_init_pstate_pmu_support(struct gk20a *g);
 
+struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g, u32 pstate_num,
+                enum nv_pmu_clk_clkwhich clkwhich);
+
 #endif /* __PSTATE_H__ */