gpu: nvgpu: gk20a: FECS HALT method

FECS halt method is used to do graceful FECS shutdown.

Bug 1551865

Change-Id: Iec8590e86cb09f9b54c36f85859208fc8650f6a6
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/682459
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 files changed, 37 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 18928142..2740129f 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics FIFO (gr host)
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -832,6 +832,9 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
         gk20a_dbg_fn("");
 
         if (engine_id == top_device_info_type_enum_graphics_v()) {
+                /*HALT_PIPELINE method, halt GR engine*/
+                if (gr_gk20a_halt_pipe(g))
+                        gk20a_err(dev_from_gk20a(g), "failed to HALT gr pipe");
                 /* resetting engine using mc_enable_r() is not enough,
                  * we do full init sequence */
                 gk20a_gr_reset(g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 75775d57..8869f4c4 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -536,6 +536,21 @@ int gr_gk20a_enable_ctxsw(struct gk20a *g)
                         gr_fecs_method_push_adr_start_ctxsw_v(), NULL);
 }
 
+int gr_gk20a_halt_pipe(struct gk20a *g)
+{
+        return gr_gk20a_submit_fecs_method_op(g,
+              (struct fecs_method_op_gk20a) {
+                      .method.addr =
+                                gr_fecs_method_push_adr_halt_pipeline_v(),
+                      .method.data = ~0,
+                      .mailbox = { .id   = 1, /*sideband?*/
+                                .data = ~0, .clr = ~0, .ret = 0,
+                                .ok   = gr_fecs_ctxsw_mailbox_value_pass_v(),
+                                .fail = gr_fecs_ctxsw_mailbox_value_fail_v(), },
+                      .cond.ok = GR_IS_UCODE_OP_EQUAL,
+                      .cond.fail = GR_IS_UCODE_OP_EQUAL });
+}
+
 
 static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va)
 {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 903b2754..0d511499 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -1,7 +1,7 @@
 /*
  * GK20A Graphics Engine
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2015, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -497,4 +497,5 @@ int gr_gk20a_alloc_gr_ctx(struct gk20a *g,
                           u32 class, u32 padding);
 void gr_gk20a_free_gr_ctx(struct gk20a *g,
                           struct vm_gk20a *vm, struct gr_ctx_desc *gr_ctx);
+int gr_gk20a_halt_pipe(struct gk20a *g);
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
index 38ffd524..7bd4ab79 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h
@@ -718,6 +718,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
 {
         return 0x21;
 }
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004;
+}
 static inline u32 gr_fecs_host_int_status_r(void)
 {
         return 0x00409c18;
@@ -1302,10 +1306,6 @@ static inline u32 gr_ds_zbc_color_r_val_f(u32 v)
 {
         return (v & 0xffffffff) << 0;
 }
-static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
-{
-        return 0x00000028;
-}
 static inline u32 gr_ds_zbc_color_g_r(void)
 {
         return 0x00405808;
@@ -1354,6 +1354,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
 {
         return 0x00000004;
 }
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028;
+}
 static inline u32 gr_ds_zbc_z_r(void)
 {
         return 0x00405818;
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index 714ceb16..23b5226a 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -718,6 +718,10 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void)
 {
         return 0x21;
 }
+static inline u32 gr_fecs_method_push_adr_halt_pipeline_v(void)
+{
+        return 0x00000004;
+}
 static inline u32 gr_fecs_host_int_status_r(void)
 {
         return 0x00409c18;
@@ -1302,6 +1306,10 @@ static inline u32 gr_ds_zbc_color_fmt_val_rf32_gf32_bf32_af32_v(void)
 {
         return 0x00000004;
 }
+static inline u32 gr_ds_zbc_color_fmt_val_a8_b8_g8_r8_v(void)
+{
+        return 0x00000028;
+}
 static inline u32 gr_ds_zbc_z_r(void)
 {
         return 0x00405818;