gpu: nvgpu: Fix sched error and recovery race

Fix race between channel recovery and sched error.

Bug 1499214

Change-Id: If95526c7e374703e8941f1b24d3916384261058e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/405662
(cherry picked from commit f8092e158294260dd9d041dc7f4d2c1872e02474)
Reviewed-on: http://git-master/r/407571
Reviewed-by: Automatic_Commit_Validation_User

2 files changed, 16 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index f1987ed5..2d2dad2c 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1101,6 +1101,15 @@ static void gk20a_fifo_trigger_mmu_fault(struct gk20a *g,
         unsigned long engine_id;
         int ret;
 
+        /*
+         * sched error prevents recovery, and ctxsw error will retrigger
+         * every 100ms. Disable the sched error to allow recovery.
+         */
+        gk20a_writel(g, fifo_intr_en_0_r(),
+                     0x7FFFFFFF & ~fifo_intr_en_0_sched_error_m());
+        gk20a_writel(g, fifo_intr_0_r(),
+                        fifo_intr_0_sched_error_reset_f());
+
         /* trigger faults for all bad engines */
         for_each_set_bit(engine_id, &engine_ids, 32) {
                 if (engine_id > g->fifo.max_engines) {
@@ -1134,6 +1143,9 @@ static void gk20a_fifo_trigger_mmu_fault(struct gk20a *g,
         /* release mmu fault trigger */
         for_each_set_bit(engine_id, &engine_ids, 32)
                 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0);
+
+        /* Re-enable sched error */
+        gk20a_writel(g, fifo_intr_en_0_r(), 0x7FFFFFFF);
 }
 
 void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
diff --git a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
index a39d3c51..5ebb8365 100644
--- a/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/hw_fifo_gk20a.h
@@ -230,6 +230,10 @@ static inline u32 fifo_intr_en_0_r(void)
 {
         return 0x00002140;
 }
+static inline u32 fifo_intr_en_0_sched_error_m(void)
+{
+        return 0x1 << 8;
+}
 static inline u32 fifo_intr_en_1_r(void)
 {
         return 0x00002528;