diff options
author | Alex Frid <afrid@nvidia.com> | 2014-08-30 02:01:46 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:08 -0400 |
commit | 3ce27f7d9a148d444dad04debff04b8f4bcb6bb6 (patch) | |
tree | 65c6184043e852e74317f02d91847d0520f5fbe8 /drivers | |
parent | 02d0e8d57449ed6a2c60dd2ec9450aafe3b8bc7a (diff) |
gpu: nvgpu: Increase GM20b debug monitor cycles
Change-Id: I913b6879e0d1ac89b740c1d088d639cc9b13b9b4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/494200
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sivaram Nair <sivaramn@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 71e21d58..1b01c74c 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -998,7 +998,7 @@ static int monitor_get(void *data, u64 *val) | |||
998 | u32 clk_slowdown, clk_slowdown_save; | 998 | u32 clk_slowdown, clk_slowdown_save; |
999 | int err; | 999 | int err; |
1000 | 1000 | ||
1001 | u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */ | 1001 | u32 ncycle = 800; /* count GPCCLK for ncycle of clkin */ |
1002 | u64 freq = clk->gpc_pll.clk_in; | 1002 | u64 freq = clk->gpc_pll.clk_in; |
1003 | u32 count1, count2; | 1003 | u32 count1, count2; |
1004 | 1004 | ||
@@ -1024,7 +1024,7 @@ static int monitor_get(void *data, u64 *val) | |||
1024 | trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle)); | 1024 | trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle)); |
1025 | /* start */ | 1025 | /* start */ |
1026 | 1026 | ||
1027 | /* It should take less than 5us to finish 100 cycle of 38.4MHz. | 1027 | /* It should take less than 25us to finish 800 cycle of 38.4MHz. |
1028 | But longer than 100us delay is required here. */ | 1028 | But longer than 100us delay is required here. */ |
1029 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); | 1029 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); |
1030 | udelay(200); | 1030 | udelay(200); |