diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-07-04 02:24:27 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 03:39:22 -0400 |
commit | 3b1ab45ccc40683c4b51dd9022c3aeed2e7666ba (patch) | |
tree | 4da431046fdeade13deb8d9abb8df60ca5c92f57 /drivers | |
parent | e808d345f11885453fc65862ec4e3dd4a375ff6d (diff) |
gpu: nvgpu: replace gk20a_dbg_* with nvgpu_dbg_*
-replace gk20a_dbg_* statements with nvgpu_dbg_*
for PMU in drivers/gpu/nvgpu/common/pmu folder
JIRA NVGPU-93
Change-Id: Id616d1f5cb5ce4007bc9543f05e57e4631cdd691
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512925
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | 21 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_pg.c | 4 |
2 files changed, 13 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index dcf6db9c..352e525f 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -221,8 +221,9 @@ static bool pmu_queue_has_room(struct nvgpu_pmu *pmu, | |||
221 | static int pmu_queue_push(struct nvgpu_pmu *pmu, | 221 | static int pmu_queue_push(struct nvgpu_pmu *pmu, |
222 | struct pmu_queue *queue, void *data, u32 size) | 222 | struct pmu_queue *queue, void *data, u32 size) |
223 | { | 223 | { |
224 | struct gk20a *g = pmu->g; | ||
224 | 225 | ||
225 | gk20a_dbg_fn(""); | 226 | nvgpu_log_fn(g, " "); |
226 | 227 | ||
227 | if (!queue->opened && queue->oflag == OFLAG_WRITE) { | 228 | if (!queue->opened && queue->oflag == OFLAG_WRITE) { |
228 | nvgpu_err(gk20a_from_pmu(pmu), "queue not opened for write"); | 229 | nvgpu_err(gk20a_from_pmu(pmu), "queue not opened for write"); |
@@ -276,7 +277,7 @@ static void pmu_queue_rewind(struct nvgpu_pmu *pmu, | |||
276 | struct gk20a *g = gk20a_from_pmu(pmu); | 277 | struct gk20a *g = gk20a_from_pmu(pmu); |
277 | struct pmu_cmd cmd; | 278 | struct pmu_cmd cmd; |
278 | 279 | ||
279 | gk20a_dbg_fn(""); | 280 | nvgpu_log_fn(g, " "); |
280 | 281 | ||
281 | if (!queue->opened) { | 282 | if (!queue->opened) { |
282 | nvgpu_err(gk20a_from_pmu(pmu), "queue not opened"); | 283 | nvgpu_err(gk20a_from_pmu(pmu), "queue not opened"); |
@@ -448,7 +449,7 @@ static int pmu_write_cmd(struct nvgpu_pmu *pmu, struct pmu_cmd *cmd, | |||
448 | struct nvgpu_timeout timeout; | 449 | struct nvgpu_timeout timeout; |
449 | int err; | 450 | int err; |
450 | 451 | ||
451 | gk20a_dbg_fn(""); | 452 | nvgpu_log_fn(g, " "); |
452 | 453 | ||
453 | queue = &pmu->queue[queue_id]; | 454 | queue = &pmu->queue[queue_id]; |
454 | nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); | 455 | nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); |
@@ -473,7 +474,7 @@ clean_up: | |||
473 | if (err) | 474 | if (err) |
474 | nvgpu_err(g, "fail to write cmd to queue %d", queue_id); | 475 | nvgpu_err(g, "fail to write cmd to queue %d", queue_id); |
475 | else | 476 | else |
476 | gk20a_dbg_fn("done"); | 477 | nvgpu_log_fn(g, "done"); |
477 | 478 | ||
478 | return err; | 479 | return err; |
479 | } | 480 | } |
@@ -489,7 +490,7 @@ int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | |||
489 | void *in = NULL, *out = NULL; | 490 | void *in = NULL, *out = NULL; |
490 | int err; | 491 | int err; |
491 | 492 | ||
492 | gk20a_dbg_fn(""); | 493 | nvgpu_log_fn(g, " "); |
493 | 494 | ||
494 | if ((!cmd) || (!seq_desc) || (!pmu->pmu_ready)) { | 495 | if ((!cmd) || (!seq_desc) || (!pmu->pmu_ready)) { |
495 | if (!cmd) | 496 | if (!cmd) |
@@ -625,12 +626,12 @@ int nvgpu_pmu_cmd_post(struct gk20a *g, struct pmu_cmd *cmd, | |||
625 | if (err) | 626 | if (err) |
626 | seq->state = PMU_SEQ_STATE_PENDING; | 627 | seq->state = PMU_SEQ_STATE_PENDING; |
627 | 628 | ||
628 | gk20a_dbg_fn("done"); | 629 | nvgpu_log_fn(g, "done"); |
629 | 630 | ||
630 | return 0; | 631 | return 0; |
631 | 632 | ||
632 | clean_up: | 633 | clean_up: |
633 | gk20a_dbg_fn("fail"); | 634 | nvgpu_log_fn(g, "fail"); |
634 | if (in) | 635 | if (in) |
635 | nvgpu_free(&pmu->dmem, | 636 | nvgpu_free(&pmu->dmem, |
636 | pv->pmu_allocation_get_dmem_offset(pmu, in)); | 637 | pv->pmu_allocation_get_dmem_offset(pmu, in)); |
@@ -650,7 +651,7 @@ static int pmu_response_handle(struct nvgpu_pmu *pmu, | |||
650 | struct pmu_v *pv = &g->ops.pmu_ver; | 651 | struct pmu_v *pv = &g->ops.pmu_ver; |
651 | int ret = 0; | 652 | int ret = 0; |
652 | 653 | ||
653 | gk20a_dbg_fn(""); | 654 | nvgpu_log_fn(g, " "); |
654 | 655 | ||
655 | seq = &pmu->seq[msg->hdr.seq_id]; | 656 | seq = &pmu->seq[msg->hdr.seq_id]; |
656 | if (seq->state != PMU_SEQ_STATE_USED && | 657 | if (seq->state != PMU_SEQ_STATE_USED && |
@@ -724,7 +725,7 @@ static int pmu_response_handle(struct nvgpu_pmu *pmu, | |||
724 | 725 | ||
725 | /* TBD: notify client waiting for available dmem */ | 726 | /* TBD: notify client waiting for available dmem */ |
726 | 727 | ||
727 | gk20a_dbg_fn("done"); | 728 | nvgpu_log_fn(g, "done"); |
728 | 729 | ||
729 | return 0; | 730 | return 0; |
730 | } | 731 | } |
@@ -734,7 +735,7 @@ static int pmu_handle_event(struct nvgpu_pmu *pmu, struct pmu_msg *msg) | |||
734 | int err = 0; | 735 | int err = 0; |
735 | struct gk20a *g = gk20a_from_pmu(pmu); | 736 | struct gk20a *g = gk20a_from_pmu(pmu); |
736 | 737 | ||
737 | gk20a_dbg_fn(""); | 738 | nvgpu_log_fn(g, " "); |
738 | switch (msg->hdr.unit_id) { | 739 | switch (msg->hdr.unit_id) { |
739 | case PMU_UNIT_PERFMON: | 740 | case PMU_UNIT_PERFMON: |
740 | case PMU_UNIT_PERFMON_T18X: | 741 | case PMU_UNIT_PERFMON_T18X: |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 06dab8ea..3cdeedcc 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c | |||
@@ -229,7 +229,7 @@ int nvgpu_pmu_disable_elpg(struct gk20a *g) | |||
229 | u32 pg_engine_id_list = 0; | 229 | u32 pg_engine_id_list = 0; |
230 | u32 *ptr = NULL; | 230 | u32 *ptr = NULL; |
231 | 231 | ||
232 | gk20a_dbg_fn(""); | 232 | nvgpu_log_fn(g, " "); |
233 | 233 | ||
234 | if (g->ops.pmu.pmu_pg_supported_engines_list) | 234 | if (g->ops.pmu.pmu_pg_supported_engines_list) |
235 | pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g); | 235 | pg_engine_id_list = g->ops.pmu.pmu_pg_supported_engines_list(g); |
@@ -483,7 +483,7 @@ int nvgpu_pmu_init_bind_fecs(struct gk20a *g) | |||
483 | int err = 0; | 483 | int err = 0; |
484 | u32 gr_engine_id; | 484 | u32 gr_engine_id; |
485 | 485 | ||
486 | gk20a_dbg_fn(""); | 486 | nvgpu_log_fn(g, " "); |
487 | 487 | ||
488 | gr_engine_id = gk20a_fifo_get_gr_engine_id(g); | 488 | gr_engine_id = gk20a_fifo_get_gr_engine_id(g); |
489 | 489 | ||