gpu: nvgpu: Clear timer registers on bus intr

Clear error address and code from timer registers. This allows
following errors to report correctly.

Change-Id: I9845ce77347ea7b9231e33f4164098cbb8694ba3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1294682
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seema Khowala <seemaj@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index a2fb8dc8..5b7f65c0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -684,6 +684,8 @@ void gk20a_pbus_isr(struct gk20a *g)
                         "NV_PGRAPH_PRI_GPC0_GPCCS_FS_GPC: 0x%x\n",
                         gk20a_readl(g, gr_gpc0_fs_gpc_r()));
 
+                gk20a_writel(g, timer_pri_timeout_save_0_r(), 0);
+                gk20a_writel(g, timer_pri_timeout_save_1_r(), 0);
         }
 
         if (val)