gpu: nvgpu: fifo ops for handling sched error and ctxsw timeout

For t19x, ctxsw timeout is not handled as part of fifo sched error
interrupt. A new fifo interrupt, ctxsw_timeout is added.

Bug 1856152
JIRA GPUT19X-74

Change-Id: I5a2ed15d967e5b14fbbb51b074080f1562bca84c
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1317599
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 15 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 08066604..c32c47fb 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -2051,7 +2051,7 @@ static bool gk20a_fifo_check_ch_ctxsw_timeout(struct channel_gk20a *ch,
         return recover;
 }
 
-static bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
+bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
                 bool *verbose, u32 *ms)
 {
         struct channel_gk20a *ch;
@@ -2121,7 +2121,7 @@ static bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
         return recover;
 }
 
-static bool gk20a_fifo_handle_sched_error(struct gk20a *g)
+bool gk20a_fifo_handle_sched_error(struct gk20a *g)
 {
         u32 sched_error;
         u32 engine_id;
@@ -2205,7 +2205,7 @@ static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr)
         }
 
         if (fifo_intr & fifo_intr_0_sched_error_pending_f()) {
-                print_channel_reset_log = gk20a_fifo_handle_sched_error(g);
+                print_channel_reset_log = g->ops.fifo.handle_sched_error(g);
                 handled |= fifo_intr_0_sched_error_pending_f();
         }
 
@@ -2463,6 +2463,9 @@ void gk20a_fifo_isr(struct gk20a *g)
                 if (fifo_intr & fifo_intr_0_pbdma_intr_pending_f())
                         clear_intr |= fifo_pbdma_isr(g, fifo_intr);
 
+                if (g->ops.fifo.handle_ctxsw_timeout)
+                        g->ops.fifo.handle_ctxsw_timeout(g, fifo_intr);
+
                 if (unlikely(fifo_intr & error_intr_mask))
                         clear_intr = fifo_error_isr(g, fifo_intr);
 
@@ -4273,4 +4276,5 @@ void gk20a_init_fifo(struct gpu_ops *gops)
         gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put;
         gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val;
         gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
+        gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
index d5456ea1..dc43c532 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h
@@ -386,4 +386,9 @@ bool gk20a_fifo_should_defer_engine_reset(struct gk20a *g, u32 engine_id,
 void gk20a_fifo_teardown_ch_tsg(struct gk20a *g, u32 __engine_ids,
                         u32 hw_id, unsigned int id_type, unsigned int rc_type,
                          struct mmu_fault_info *mmfault);
+
+bool gk20a_fifo_check_tsg_ctxsw_timeout(struct tsg_gk20a *tsg,
+                        bool *verbose, u32 *ms);
+bool gk20a_fifo_handle_sched_error(struct gk20a *g);
+
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index aeef263e..e4450185 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -472,6 +472,8 @@ struct gpu_ops {
                 void (*teardown_ch_tsg)(struct gk20a *g, u32 act_eng_bitmask,
                         u32 id, unsigned int id_type, unsigned int rc_type,
                          struct mmu_fault_info *mmfault);
+                bool (*handle_sched_error)(struct gk20a *g);
+                bool (*handle_ctxsw_timeout)(struct gk20a *g, u32 fifo_intr);
         } fifo;
         struct pmu_v {
                 /*used for change of enum zbc update cmd id from ver 0 to ver1*/
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 22ff3629..2f705004 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -228,4 +228,5 @@ void gm20b_init_fifo(struct gpu_ops *gops)
         gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs;
         gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw;
         gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg;
+        gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error;
 }