diff options
author | Srikar Srimath Tirumala <srikars@nvidia.com> | 2016-12-15 22:42:42 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-12-21 02:05:56 -0500 |
commit | 34d8421ab4e9ecd0af09f7fefe71b9a1d8781061 (patch) | |
tree | 2e728df78c393280b7a6207c58ffe697009b7ab9 /drivers | |
parent | 23f9dddbb6c5f3e922addd2f286ad86b710c5573 (diff) |
gpu: nvgpu: fix round_rate ops for CCF
Make round_rate return max freq when called with a value greater than
the max clock frequency.
Bug 200233943
Change-Id: Id128611f2d09b17a0a0edfefd4b526fd8c215bce
Signed-off-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Reviewed-on: http://git-master/r/1272305
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
Tested-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_common.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 4 |
2 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_common.c b/drivers/gpu/nvgpu/clk/clk_common.c index 346ad12b..529efa15 100644 --- a/drivers/gpu/nvgpu/clk/clk_common.c +++ b/drivers/gpu/nvgpu/clk/clk_common.c | |||
@@ -45,6 +45,7 @@ unsigned long gk20a_clk_get_rate(struct gk20a *g) | |||
45 | return rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | 45 | return rate_gpc2clk_to_gpu(clk->gpc_pll.freq); |
46 | } | 46 | } |
47 | 47 | ||
48 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
48 | long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate) | 49 | long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate) |
49 | { | 50 | { |
50 | /* make sure the clock is available */ | 51 | /* make sure the clock is available */ |
@@ -54,6 +55,17 @@ long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate) | |||
54 | return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate); | 55 | return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate); |
55 | } | 56 | } |
56 | 57 | ||
58 | #else | ||
59 | long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate) | ||
60 | { | ||
61 | /* make sure the clock is available */ | ||
62 | if (!gk20a_clk_get(g)) | ||
63 | return rate; | ||
64 | |||
65 | return clk_round_rate(g->clk.tegra_clk, rate); | ||
66 | } | ||
67 | #endif | ||
68 | |||
57 | int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate) | 69 | int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate) |
58 | { | 70 | { |
59 | return clk_set_rate(g->clk.tegra_clk, rate); | 71 | return clk_set_rate(g->clk.tegra_clk, rate); |
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 060a5775..b1ea7331 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1305,8 +1305,12 @@ static long gm20b_round_rate(struct clk_hw *hw, unsigned long rate, | |||
1305 | { | 1305 | { |
1306 | struct clk_gk20a *clk = to_clk_gk20a(hw); | 1306 | struct clk_gk20a *clk = to_clk_gk20a(hw); |
1307 | u32 freq, old_freq; | 1307 | u32 freq, old_freq; |
1308 | unsigned long maxrate; | ||
1308 | struct pll tmp_pll; | 1309 | struct pll tmp_pll; |
1309 | 1310 | ||
1311 | maxrate = tegra_dvfs_get_maxrate(hw->clk); | ||
1312 | gpc_pll_params.max_freq = rate_gpu_to_gpc2clk(maxrate); | ||
1313 | |||
1310 | mutex_lock(&clk->clk_mutex); | 1314 | mutex_lock(&clk->clk_mutex); |
1311 | old_freq = clk->gpc_pll.freq; | 1315 | old_freq = clk->gpc_pll.freq; |
1312 | freq = rate_gpu_to_gpc2clk(rate); | 1316 | freq = rate_gpu_to_gpc2clk(rate); |