gpu: nvgpu: Disable channel when updating SMPC WAR

When updating SMPC WAR for channel, it needs to be kicked out. This
ensures that the updated information is re-read from context header.

Bug 1579548

Change-Id: Ia65bdb638cec7125021a8e60c365b83085efe0d4
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/741322
Reviewed-on: http://git-master/r/743859
(cherry picked from commit dd6cd54b41d63ae94d066b8d98a40c6f6a2196e5)
Reviewed-on: http://git-master/r/753283
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 603fc3a4..b2fea5b8 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -1566,6 +1566,15 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
         struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
         void *ctx_ptr = NULL;
         u32 data;
+        int ret;
+
+        c->g->ops.fifo.disable_channel(c);
+        ret = c->g->ops.fifo.preempt_channel(c->g, c->hw_chid);
+        if (ret) {
+                gk20a_err(dev_from_gk20a(g),
+                        "failed to preempt channel\n");
+                return ret;
+        }
 
         /* Channel gr_ctx buffer is gpu cacheable.
            Flush and invalidate before cpu update. */
@@ -1587,6 +1596,11 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g,
 
         vunmap(ctx_ptr);
 
+        /* enable channel */
+        gk20a_writel(c->g, ccsr_channel_r(c->hw_chid),
+                gk20a_readl(c->g, ccsr_channel_r(c->hw_chid)) |
+                ccsr_channel_enable_set_true_f());
+
         return 0;
 }