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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-12-20 18:14:16 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-01-04 04:44:24 -0500
commit2a95a288b285b0eff16a8825298c416d185693fb (patch)
tree8040b60aa5761b638f08cc1032feb0f729ed57ae /drivers
parentfef7083e516ff6da4681ea8aaeedc114c6f2c821 (diff)
gpu: nvgpu: Check reference clock before use
We use GPU reference clock as a divider. Check before division that reference clock is not zero. Change-Id: Ie453a78b422b2e740daeb7c12ce5b06faa52ba76 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1275743 GVS: Gerrit_Virtual_Submit Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/clk_gk20a.c5
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c5
2 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
index 2c4f1bf4..34f3f886 100644
--- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.c
@@ -439,6 +439,11 @@ static int gk20a_init_clk_setup_sw(struct gk20a *g)
439 439
440 clk->gpc_pll.id = GK20A_GPC_PLL; 440 clk->gpc_pll.id = GK20A_GPC_PLL;
441 clk->gpc_pll.clk_in = ref_rate / KHZ; 441 clk->gpc_pll.clk_in = ref_rate / KHZ;
442 if (clk->gpc_pll.clk_in == 0) {
443 gk20a_err(dev_from_gk20a(g),
444 "GPCPLL reference clock is zero");
445 return -EINVAL;
446 }
442 447
443 /* Decide initial frequency */ 448 /* Decide initial frequency */
444 if (!initialized) { 449 if (!initialized) {
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 906e805a..3fa5c1d3 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -1158,6 +1158,11 @@ static int gm20b_init_gpc_pll(struct gk20a *g)
1158 1158
1159 clk->gpc_pll.id = GK20A_GPC_PLL; 1159 clk->gpc_pll.id = GK20A_GPC_PLL;
1160 clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; 1160 clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ;
1161 if (clk->gpc_pll.clk_in == 0) {
1162 gk20a_err(dev_from_gk20a(g),
1163 "GPCPLL reference clock is zero");
1164 return -EINVAL;
1165 }
1161 1166
1162 gm20b_calc_dvfs_safe_max_freq(c); 1167 gm20b_calc_dvfs_safe_max_freq(c);
1163 clk->gpc_pll.PL = (dvfs_safe_max_freq == 0) ? 0 : 1168 clk->gpc_pll.PL = (dvfs_safe_max_freq == 0) ? 0 :