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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-11-08 16:36:17 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2016-11-11 11:21:06 -0500
commit268e772e807460cee64e354c025d43d8e24574b8 (patch)
treef2f4232c4530070f238c95759ad7f2eb5a9f1d14 /drivers
parentc30f649c4f85929580490180122a1e8c5edb6098 (diff)
gpu: nvgpu: Deal with invalid MMU id
If gk20a_engine_id_to_mmu_id() fails, it returns ~0. Deal with this by checking the results in each call to it. Change-Id: I6fb9f7151f21a6c4694bfb2ea3c960d344fe629f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1249965 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c23
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c9
2 files changed, 19 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index b4850ee3..9887b68f 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1557,15 +1557,18 @@ static void gk20a_fifo_trigger_mmu_fault(struct gk20a *g,
1557 1557
1558 /* trigger faults for all bad engines */ 1558 /* trigger faults for all bad engines */
1559 for_each_set_bit(engine_id, &engine_ids, 32) { 1559 for_each_set_bit(engine_id, &engine_ids, 32) {
1560 u32 mmu_id;
1561
1560 if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) { 1562 if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) {
1561 WARN_ON(true); 1563 WARN_ON(true);
1562 break; 1564 break;
1563 } 1565 }
1564 1566
1565 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 1567 mmu_id = gk20a_engine_id_to_mmu_id(g, engine_id);
1566 fifo_trigger_mmu_fault_id_f( 1568 if (mmu_id != ~0)
1567 gk20a_engine_id_to_mmu_id(g, engine_id)) | 1569 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id),
1568 fifo_trigger_mmu_fault_enable_f(1)); 1570 fifo_trigger_mmu_fault_id_f(mmu_id) |
1571 fifo_trigger_mmu_fault_enable_f(1));
1569 } 1572 }
1570 1573
1571 /* Wait for MMU fault to trigger */ 1574 /* Wait for MMU fault to trigger */
@@ -1707,8 +1710,10 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
1707 /* atleast one engine will get passed during sched err*/ 1710 /* atleast one engine will get passed during sched err*/
1708 engine_ids |= __engine_ids; 1711 engine_ids |= __engine_ids;
1709 for_each_set_bit(engine_id, &engine_ids, 32) { 1712 for_each_set_bit(engine_id, &engine_ids, 32) {
1710 mmu_fault_engines |= 1713 u32 mmu_id = gk20a_engine_id_to_mmu_id(g, engine_id);
1711 BIT(gk20a_engine_id_to_mmu_id(g, engine_id)); 1714
1715 if (mmu_id != ~0)
1716 mmu_fault_engines |= BIT(mmu_id);
1712 } 1717 }
1713 } else { 1718 } else {
1714 /* store faulted engines in advance */ 1719 /* store faulted engines in advance */
@@ -1728,9 +1733,11 @@ void gk20a_fifo_recover(struct gk20a *g, u32 __engine_ids,
1728 1733
1729 gk20a_fifo_get_faulty_id_type(g, active_engine_id, &id, &type); 1734 gk20a_fifo_get_faulty_id_type(g, active_engine_id, &id, &type);
1730 if (ref_type == type && ref_id == id) { 1735 if (ref_type == type && ref_id == id) {
1736 u32 mmu_id = gk20a_engine_id_to_mmu_id(g, active_engine_id);
1737
1731 engine_ids |= BIT(active_engine_id); 1738 engine_ids |= BIT(active_engine_id);
1732 mmu_fault_engines |= 1739 if (mmu_id != ~0)
1733 BIT(gk20a_engine_id_to_mmu_id(g, active_engine_id)); 1740 mmu_fault_engines |= BIT(mmu_id);
1734 } 1741 }
1735 } 1742 }
1736 } 1743 }
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index a8934035..3b877db1 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -74,16 +74,15 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
74 74
75 /* trigger faults for all bad engines */ 75 /* trigger faults for all bad engines */
76 for_each_set_bit(engine_id, &engine_ids, 32) { 76 for_each_set_bit(engine_id, &engine_ids, 32) {
77 u32 engine_mmu_fault_id;
78
79 if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) { 77 if (!gk20a_fifo_is_valid_engine_id(g, engine_id)) {
80 gk20a_err(dev_from_gk20a(g), 78 gk20a_err(dev_from_gk20a(g),
81 "faulting unknown engine %ld", engine_id); 79 "faulting unknown engine %ld", engine_id);
82 } else { 80 } else {
83 engine_mmu_fault_id = gm20b_engine_id_to_mmu_id(g, 81 u32 mmu_id = gm20b_engine_id_to_mmu_id(g,
84 engine_id); 82 engine_id);
85 gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 83 if (mmu_id != ~0)
86 fifo_trigger_mmu_fault_enable_f(1)); 84 gk20a_writel(g, fifo_trigger_mmu_fault_r(mmu_id),
85 fifo_trigger_mmu_fault_enable_f(1));
87 } 86 }
88 } 87 }
89 88