gpu: nvgpu: HAL to write DMATRFBASE

Bug 200137618

Change-Id: I18b980876e93c3f7287082701e1d2b998cd33114
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/798777
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

3 files changed, 16 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index d48b94aa..dd7a7ad4 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -390,6 +390,7 @@ struct gpu_ops {
                 int (*pmu_setup_elpg)(struct gk20a *g);
                 int (*init_wpr_region)(struct gk20a *g);
                 int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask);
+                void (*write_dmatrfbase)(struct gk20a *g, u32 addr);
                 u32  lspmuwprinitdone;
                 u32  lsfloadedfalconid;
                 bool fecsbootstrapdone;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 18404ec0..110f3c5a 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -1763,8 +1763,8 @@ static int pmu_bootstrap(struct pmu_gk20a *pmu)
         gk20a_writel(g, pwr_falcon_dmemd_r(0), 0x1);
         gk20a_writel(g, pwr_falcon_dmemd_r(0), addr_args);
 
-        gk20a_writel(g, pwr_falcon_dmatrfbase_r(),
-                addr_load - (desc->bootloader_imem_offset >> 8));
+        g->ops.pmu.write_dmatrfbase(g,
+                        addr_load - (desc->bootloader_imem_offset >> 8));
 
         blocks = ((desc->bootloader_size + 0xFF) & ~0xFF) >> 8;
 
@@ -2643,6 +2643,11 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g)
         }
 }
 
+static void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr)
+{
+        gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr);
+}
+
 void gk20a_init_pmu_ops(struct gpu_ops *gops)
 {
         gops->pmu.prepare_ucode = gk20a_prepare_ucode;
@@ -2651,6 +2656,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.pmu_setup_elpg = NULL;
         gops->pmu.init_wpr_region = NULL;
         gops->pmu.load_lsfalcon_ucode = NULL;
+        gops->pmu.write_dmatrfbase = gk20a_write_dmatrfbase;
 }
 
 int gk20a_init_pmu_support(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 813bb16c..9cf9cb26 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -19,6 +19,7 @@
 #include "acr_gm20b.h"
 #include "pmu_gm20b.h"
 #include "hw_gr_gm20b.h"
+#include "hw_pwr_gm20b.h"
 
 /*!
  * Structure/object which single register write need to be done during PG init
@@ -283,6 +284,11 @@ static int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
         return err;
 }
 
+static void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr)
+{
+        gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr);
+}
+
 void gm20b_init_pmu_ops(struct gpu_ops *gops)
 {
         if (gops->privsecurity) {
@@ -299,4 +305,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg;
         gops->pmu.lspmuwprinitdone = 0;
         gops->pmu.fecsbootstrapdone = false;
+        gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase;
 }