diff options
author | Alex Frid <afrid@nvidia.com> | 2017-06-14 21:49:05 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-25 15:54:48 -0400 |
commit | 20d1b9a40db337c1d9b83aaacd03336932c19e5f (patch) | |
tree | a71b61e6c4d41b0b31133ce5af0cf9de80318cad /drivers | |
parent | 66ec347db401affd8bcd425dc123e7162b9ae3bb (diff) |
gpu: nvgpu: Change GPCPLL rev C1 control settings
Updated DFS control settings for GPCPLL revision C1 per characterization
data.
Bug 1942222
Change-Id: Iab5147e13ef70df980d36589328abafd8f5495b8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1502741
(cherry picked from commit 5ea62c9e264de86f6e5a40a7f31054ab31b3196f)
Reviewed-on: https://git-master.nvidia.com/r/1525830
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 18 |
2 files changed, 16 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index e8c14e43..23e57ed4 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h | |||
@@ -77,6 +77,8 @@ struct pll_parms { | |||
77 | u32 lock_timeout; | 77 | u32 lock_timeout; |
78 | u32 na_lock_delay; | 78 | u32 na_lock_delay; |
79 | u32 iddq_exit_delay; | 79 | u32 iddq_exit_delay; |
80 | /* NA mode DFS control */ | ||
81 | u32 dfs_ctrl; | ||
80 | }; | 82 | }; |
81 | 83 | ||
82 | struct namemap_cfg; | 84 | struct namemap_cfg; |
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index e28a31c8..addc27bb 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -71,6 +71,7 @@ static struct pll_parms gpc_pll_params_c1 = { | |||
71 | 500, /* Locking and ramping timeout */ | 71 | 500, /* Locking and ramping timeout */ |
72 | 40, /* Lock delay in NA mode */ | 72 | 40, /* Lock delay in NA mode */ |
73 | 5, /* IDDQ mode exit delay */ | 73 | 5, /* IDDQ mode exit delay */ |
74 | 0x3 << 10, /* DFS control settings */ | ||
74 | }; | 75 | }; |
75 | 76 | ||
76 | static struct pll_parms gpc_pll_params; | 77 | static struct pll_parms gpc_pll_params; |
@@ -411,7 +412,7 @@ static void __maybe_unused clk_set_dfs_det_max(struct gk20a *g, u32 dfs_det_max) | |||
411 | 412 | ||
412 | static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal) | 413 | static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal) |
413 | { | 414 | { |
414 | u32 data; | 415 | u32 data, ctrl; |
415 | 416 | ||
416 | data = gk20a_readl(g, trim_gpc_bcast_gpcpll_dvfs2_r()); | 417 | data = gk20a_readl(g, trim_gpc_bcast_gpcpll_dvfs2_r()); |
417 | data &= ~(BIT(DFS_DET_RANGE + 1) - 1); | 418 | data &= ~(BIT(DFS_DET_RANGE + 1) - 1); |
@@ -420,10 +421,11 @@ static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal) | |||
420 | 421 | ||
421 | data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); | 422 | data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); |
422 | nvgpu_udelay(1); | 423 | nvgpu_udelay(1); |
423 | if (~trim_sys_gpcpll_dvfs1_dfs_ctrl_v(data) & DFS_EXT_CAL_EN) { | 424 | ctrl = trim_sys_gpcpll_dvfs1_dfs_ctrl_v(data); |
425 | if (~ctrl & DFS_EXT_CAL_EN) { | ||
424 | data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(), | 426 | data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(), |
425 | trim_sys_gpcpll_dvfs1_dfs_ctrl_f( | 427 | trim_sys_gpcpll_dvfs1_dfs_ctrl_f( |
426 | DFS_EXT_CAL_EN | DFS_TESTOUT_DET)); | 428 | ctrl | DFS_EXT_CAL_EN | DFS_TESTOUT_DET)); |
427 | gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data); | 429 | gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data); |
428 | } | 430 | } |
429 | } | 431 | } |
@@ -472,6 +474,14 @@ static int clk_enbale_pll_dvfs(struct gk20a *g) | |||
472 | gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data); | 474 | gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data); |
473 | } | 475 | } |
474 | 476 | ||
477 | /* Set NA mode DFS control */ | ||
478 | if (p->dfs_ctrl) { | ||
479 | data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); | ||
480 | data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(), | ||
481 | trim_sys_gpcpll_dvfs1_dfs_ctrl_f(p->dfs_ctrl)); | ||
482 | gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data); | ||
483 | } | ||
484 | |||
475 | /* | 485 | /* |
476 | * If calibration parameters are known (either from fuses, or from | 486 | * If calibration parameters are known (either from fuses, or from |
477 | * internal calibration on boot) - use them. Internal calibration is | 487 | * internal calibration on boot) - use them. Internal calibration is |