gpu: nvgpu: create a hal function for smpc war

Create a HAL function for applying the SMPC workaround.The workaround
is only needed on gk20a, and not on gm20b.

Change-Id: I9edc741df32ab7d1dad38ecc56f238828128bfef
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/539187
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 50 insertions, 32 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
index 6af54e68..94486064 100644
--- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c
@@ -686,39 +686,8 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
                           "error (%d) during smpc ctxsw mode update\n", err);
                 goto clean_up;
         }
-        /* The following regops are a hack/war to make up for the fact that we
-         * just scribbled into the ctxsw image w/o really knowing whether
-         * it was already swapped out in/out once or not, etc.
-         */
-        {
-                struct nvgpu_dbg_gpu_reg_op ops[4];
-                int i;
-                for (i = 0; i < ARRAY_SIZE(ops); i++) {
-                        ops[i].op     = NVGPU_DBG_GPU_REG_OP_WRITE_32;
-                        ops[i].type   = NVGPU_DBG_GPU_REG_OP_TYPE_GR_CTX;
-                        ops[i].status = NVGPU_DBG_GPU_REG_OP_STATUS_SUCCESS;
-                        ops[i].value_hi      = 0;
-                        ops[i].and_n_mask_lo = 0;
-                        ops[i].and_n_mask_hi = 0;
-                }
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/
-                ops[0].offset   = 0x00419e08;
-                ops[0].value_lo = 0x1d;
-
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */
-                ops[1].offset   = 0x00419e58;
-                ops[1].value_lo = 0x1;
 
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */
-                ops[2].offset   = 0x00419e68;
-                ops[2].value_lo = 0xaaaa;
-
-                /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */
-                ops[3].offset   = 0x00419f40;
-                ops[3].value_lo = 0x18;
-
-                err = dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops));
-        }
+        err = g->ops.regops.apply_smpc_war(dbg_s);
 
  clean_up:
         mutex_unlock(&g->dbg_sessions_lock);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index a111a040..28d43081 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -335,6 +335,7 @@ struct gpu_ops {
                 const struct regop_offset_range* (
                                 *get_qctl_whitelist_ranges)(void);
                 int (*get_qctl_whitelist_ranges_count)(void);
+                int (*apply_smpc_war)(struct dbg_session_gk20a *dbg_s);
         } regops;
         struct {
                 void (*intr_enable)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
index 7adb458b..d9984e03 100644
--- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c
@@ -757,6 +757,42 @@ int gk20a_get_qctl_whitelist_ranges_count(void)
         return gk20a_qctl_whitelist_ranges_count;
 }
 
+int gk20a_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
+{
+        /* The following regops are a hack/war to make up for the fact that we
+         * just scribbled into the ctxsw image w/o really knowing whether
+         * it was already swapped out in/out once or not, etc.
+         */
+        struct nvgpu_dbg_gpu_reg_op ops[4];
+        int i;
+        for (i = 0; i < ARRAY_SIZE(ops); i++) {
+                ops[i].op     = REGOP(WRITE_32);
+                ops[i].type   = REGOP(TYPE_GR_CTX);
+                ops[i].status = REGOP(STATUS_SUCCESS);
+                ops[i].value_hi      = 0;
+                ops[i].and_n_mask_lo = 0;
+                ops[i].and_n_mask_hi = 0;
+        }
+
+        /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control_sel1_r();*/
+        ops[0].offset   = 0x00419e08;
+        ops[0].value_lo = 0x1d;
+
+        /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control5_r(); */
+        ops[1].offset   = 0x00419e58;
+        ops[1].value_lo = 0x1;
+
+        /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter_control3_r(); */
+        ops[2].offset   = 0x00419e68;
+        ops[2].value_lo = 0xaaaa;
+
+        /* gr_pri_gpcs_tpcs_sm_dsm_perf_counter4_control_r(); */
+        ops[3].offset   = 0x00419f40;
+        ops[3].value_lo = 0x18;
+
+        return dbg_s->ops->exec_reg_ops(dbg_s, ops, ARRAY_SIZE(ops));
+}
+
 void gk20a_init_regops(struct gpu_ops *gops)
 {
         gops->regops.get_global_whitelist_ranges =
@@ -788,4 +824,7 @@ void gk20a_init_regops(struct gpu_ops *gops)
                 gk20a_get_qctl_whitelist_ranges;
         gops->regops.get_qctl_whitelist_ranges_count =
                 gk20a_get_qctl_whitelist_ranges_count;
+
+        gops->regops.apply_smpc_war =
+                gk20a_apply_smpc_war;
 }
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
index b7cc0aaa..71ccda37 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
@@ -494,6 +494,12 @@ int gm20b_get_qctl_whitelist_ranges_count(void)
         return gm20b_qctl_whitelist_ranges_count;
 }
 
+int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
+{
+        /* Not needed on gm20b */
+        return 0;
+}
+
 void gm20b_init_regops(struct gpu_ops *gops)
 {
         gops->regops.get_global_whitelist_ranges =
@@ -525,4 +531,7 @@ void gm20b_init_regops(struct gpu_ops *gops)
                 gm20b_get_qctl_whitelist_ranges;
         gops->regops.get_qctl_whitelist_ranges_count =
                 gm20b_get_qctl_whitelist_ranges_count;
+
+        gops->regops.apply_smpc_war =
+                gm20b_apply_smpc_war;
 }